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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | AD5765CSUZ |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 26/28闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC DAC 16BIT QUAD 5V 1LSB 32TQFP |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Data Converter Fundamentals DAC Architectures |
| 鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� | AD5763/65 Metal Layer Edit Change 08/Sept/2009 |
| 瑷�(sh猫)瑷堣硣婧愶細 | High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion Using AD5765 (CN0073) |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 瑷�(sh猫)缃檪闁擄細 | 8µs |
| 浣嶆暩(sh霉)锛� | 16 |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶 |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 4 |
| 闆诲闆绘簮锛� | 闆� ± |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 76mW |
| 宸ヤ綔婧害锛� | -40°C ~ 105°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 32-TQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 32-TQFP锛�7x7锛� |
| 鍖呰锛� | 鎵樼洡 |
| 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷锛� | 4 闆诲锛岄洐妤� |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | * |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 784 (CN2011-ZH PDF) |
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Data Sheet
AD5765
Rev. C | Page 7 of 28
TIMING CHARACTERISTICS
AVDD = 4.75 V to 5.25 V, AVSS = 4.75 V to 5.25 V, AGNDx = DGND = REFGND = PGND = 0 V, REFAB = REFCD = 2.048 V,
DVCC = 2.7 V to 5.25 V, RLOAD = 5 k, CLOAD = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1, 2, 3
Limit at TMIN, TMAX
Unit
Description
t1
33
ns min
SCLK cycle time
t2
13
ns min
SCLK high time
t3
13
ns min
SCLK low time
t4
13
ns min
SYNC falling edge to SCLK falling edge setup time
t54
13
ns min
24th SCLK falling edge to SYNC rising edge
t6
90
ns min
Minimum SYNC high time
t7
2
ns min
Data setup time
t8
5
ns min
Data hold time
t9
1.7
s min
SYNC rising edge to LDAC falling edge when all DACs are updated
480
ns min
SYNC rising edge to LDAC falling edge when a single DAC is updated
t10
10
ns min
LDAC pulse width low
t11
500
ns max
LDAC falling edge to DAC output response time
t12
10
s max
DAC output settling time
t13
10
ns min
CLR pulse width low
t14
2
s max
CLR pulse activation time
25
ns max
SCLK rising edge to SDO valid
t16
13
ns min
SYNC rising edge to SCLK falling edge
t17
2
s max
SYNC rising edge to DAC output response time (LDAC = 0)
t18
170
ns min
LDAC falling edge to SYNC rising edge
1
Guaranteed by design and characterization; not production tested.
2
All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3
4
Standalone mode only.
5
Measured with the load circuit of Figure 5.
6
Daisy-chain mode only.
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