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| 型號： | AD604-EVALZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/33頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD604 AMP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | X-AMP® |
| 每 IC 通道數(shù)： | 2 - 雙 |
| 放大器類型： | 可變增益 |
| 輸出類型： | 單端 |
| 轉(zhuǎn)換速率： | 170 V/µs |
| -3db帶寬： | 40MHz |
| 電流 - 輸出 / 通道： | 40mA |
| 工作溫度： | -40°C ~ 85°C |
| 電流供應(yīng)（主 IC）： | 32mA |
| 板類型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD604 |
| 相關(guān)產(chǎn)品： | AD604ARZ-RL-ND - IC AMP VGA DUAL ULN 40MA 24SOIC AD604ANZ-ND - IC AMP VGA DUAL ULN 40MA 24DIP AD604ARSZ-R7-ND - IC AMP VGA DUAL ULN 40MA 24SSOP AD604ARSZ-RL-ND - IC AMP VGA DUAL ULN 40MA 24SSOP AD604ARSZ-ND - IC AMP VGA DUAL ULN 40MA 24SSOP AD604ARZ-ND - IC AMP VGA DUAL ULN 40MA 24SOIC AD604AR-REEL-ND - IC AMP VGA DUAL ULN 40MA 24SOIC AD604AR-ND - IC AMP VGA DUAL ULN 40MA 24SOIC |
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AD604
Rev. G | Page 20 of 32
The 50 Ω termination resistor, in parallel with the 50 Ω source
resistance of the signal generator, forms an effective resistance of
25 Ω as seen by the input of the preamplifier, creating 4.07 μV of
rms noise at a bandwidth of 40 MHz. The noise floor of this
channel is consequently 6.5 μV rms, the rms sum of these two
main noise sources. The minimum detectable signal (MDS) for
this circuit is +6.5 μV rms (90.7 dBm). Generally, the measured
signal should be about a factor of three larger than the noise
floor, in this case 19.5 μV rms. Note that the 25 μV rms signal
that this AGC circuit can correct for is just slightly above the
MDS. Of course, the sensitivity of the input can be improved by
band-limiting the signal; if the noise bandwidth is reduced by a
factor of four to 10 MHz, the noise floor of the AGC circuit with a
50 Ω termination resistor drops to +3.25 μV rms (96.7 dBm).
Further noise improvement can be achieved by an input matching
network or by transformer coupling of the input signal.
VGN (V)
90
80
–30
70
60
20
50
40
30
–20
–10
0
10
GA
IN
(
d
B
)
f =1MHz
0.1
0.5
0.9
1.3
1.7
2.1
2.5
2.9
00
54
0-
04
5
Figure 45. Cascaded Gain vs. VGN (Based on Figure 44)
VGN (V)
4
3
–4
2
1
–3
0
–1
–2
G
AI
N
E
RR
O
R
(
d
B)
f =1MHz
0.2
0.7
1.2
1.7
2.2
2.7
00
54
0-
0
46
Figure 46. Cascaded Gain Error vs. VGN (Based on Figure 44)
The descriptions of the detector circuitry functions, comprising
a squarer, a low-pass filter, and an integrator, follow. At this
point, it is necessary to make some assumptions about the input
signal. The following explanation of the detector circuitry presumes
an amplitude modulated RF carrier where the modulating signal is
at a much lower frequency than the RF signal. The AD835
multiplier functions as the detector by squaring the output signal
presented to it by the AD604. A low-pass filter following the
squaring operation removes the RF signal component at twice
the incoming signal frequency, while passing the low frequency
AM information. The following integrator with a time constant of
2 ms set by R8 and C11 integrates the error signal presented by
the low-pass filter and changes VG until the error signal is equal
to VSET.
For example, if the signal presented to the detector is V1 = A ×
cos(ωt) as indicated in Figure 44, the output of the squarer is
(V1)2/1 V. The reason for all the minus signs in the detection
circuitry is the necessity of providing negative feedback in the
control loop; actually, if VSET becomes greater than 0 V, the
control loop provides positive feedback. Squaring A × cos(ωt)
results in two terms, one at dc and one at 2ω; the following low-
pass filter passes only the (A)2/2 dc term. This dc voltage is
now forced equal to the voltage, VSET, by the control loop. The
squarer, together with the low-pass filter, functions as a mean-
square detector. As should be evident by controlling the value of
VSET, the amplitude of the voltage V1 can be set at the input of
amplitude is ±400 mV.
Figure 47 shows the control voltage, VGN, vs. the input power at
frequencies of 1 MHz (solid line) and 10 MHz (dashed line) at
an output regulated level of 2 dBm (800 mV p-p). The AGC
threshold is evident at a PIN of about 79 dBm; the highest input
power that can still be accommodated is about +3 dBm. At this
level, the output starts being distorted because of clipping in the
preamplifier.
4.5
4.0
0.5
3.5
3.0
1.0
2.5
2.0
1.5
CO
NT
RO
L
V
O
L
T
AG
E
(
V
)
1MHz
10MHz
PIN (dBm)
–80
–70
–60
–50
–40
–30
–20
–10
0
10
00
54
0-
0
47
Figure 47. Control Voltage vs. Input Power of the Circuit in Figure 44
As previously mentioned, the second preamplifier can be used
shows the modifications that must be made to Figure 46 to achieve
96 dB of gain and dynamic range. Because of the extremely high
gain, the bandwidth must be limited to reject some of the noise.
Furthermore, limiting the bandwidth helps suppress high-
frequency oscillations. The added components act as a low-pass
filter and dc block (C5 decouples the 2.5 V common-mode
output of the first DSX). The ferrite bead has an impedance of
about 5 Ω at 1 MHz, 30 Ω at 10 MHz, and 70 Ω at 100 MHz.
The bead, combined with R2 and C6, forms a 1 MHz low-pass
filter.
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