參數資料
| 型號： | AD623BRZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 10/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP INST R-R LP 8SOIC |
| 標準包裝： | 2,500 |
| 放大器類型： | 儀表 |
| 電路數： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉換速率： | 0.3 V/µs |
| -3db帶寬： | 800kHz |
| 電流 - 輸入偏壓： | 17nA |
| 電壓 - 輸入偏移： | 25µV |
| 電流 - 電源： | 375µA |
| 電壓 - 電源，單路/雙路(±)： | 2.7 V ~ 12 V，± 2.5 V ~ 6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
AD623
Rev. D | Page 18 of 24
The circuit in Figure 45 should be built using a PC board with a
ground plane on both sides. All component leads should be as
short as possible. Resistors R1 and R2 can be common 1% metal
film units, but Capacitors C1 and C2 need to be ±5% tolerance
devices to avoid degrading the circuit’s common-mode rejection.
Either the traditional 5% silver mica units or Panasonic ±2%
PPS film capacitors are recommended.
In many applications, shielded cables are used to minimize
noise; for best CMR over frequency, the shield should be properly
driven. Figure 46 shows an active guard driver that is configured
to improve ac common-mode rejection by bootstrapping the
capacitances of input cable shields, thus minimizing the capacitance
mismatch between the inputs.
AD623
OUTPUT
REF
+VS
–VS
2
1
8
3
6
5
7
4
RG
2
RG
2
AD8031
100
0
07
78
-04
5
–IN
+IN
Figure 46. Common-Mode Shield Driver
GROUNDING
Because the AD623 output voltage is developed with respect to
the potential on the reference terminal, many grounding problems
can be solved by simply tying the REF pin to the appropriate local
ground. The REF pin should, however, be tied to a low impedance
point for optimal CMR.
The use of ground planes is recommended to minimize the
impedance of ground returns (and hence the size of dc errors).
To isolate low level analog signals from a noisy digital environment,
many data acquisition components have separate analog and
digital ground returns (see Figure 47). All ground pins from
mixed signal components, such as analog-to-digital converters
(ADCs), should be returned through the high quality analog
ground plane. Maximum isolation between analog and digital is
achieved by connecting the ground planes back at the supplies.
The digital return currents from the ADC that flow in the analog
ground plane, in general, have a negligible effect on noise
performance.
If there is only a single power supply available, it must be shared
by both digital and analog circuitry. Figure 48 shows how to
minimize interference between the digital and analog circuitry.
As in the previous case, separate analog and digital ground planes
should be used (reasonably thick traces can be used as an
alternative to a digital ground plane). These ground planes
should be connected at the ground pin of the power supply.
Separate traces should be run from the power supply to the
supply pins of the digital and analog circuits. Ideally, each device
should have its own power supply trace, but these can be shared
by a number of devices, as long as a single trace is not used to
route current to both digital and analog circuitry.
AGND
VDD
MICROPROCESSOR
AD623
2
3
6
5
7
4
ANALOG POWER SUPPLY
GND
–5V
+5V
DIGITAL POWER SUPPLY
+5V
GND
4
VIN1
1
VDD
6
AGND
14
DGND
3
VIN2
ADC
AD7892-2
0.1F
0.1F 0.1F
12
0
07
78
-04
6
Figure 47. Optimal Grounding Practice for a Bipolar Supply Environment with Separate Analog and Digital Supplies
AGND
VDD
MICROPROCESSOR
AD623
2
3
6
5
7
4
VIN1
1
VDD
6
AGND
14
DGND
ADC
AD7892-2
0.1F
12
POWER SUPPLY
+5V
GND
0
07
78
-04
7
Figure 48. Optimal Ground Practice in a Single Supply Environment
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