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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD6472
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1998
2 Pair/1 Pair ETSI Compatible
HDSL Analog Front End
FUNCT IONAL BLOCK DIAGRAM
CONTROL
LOGIC
12-BIT
DAC
2
7-BIT
DAC
12-BIT
ADC
2
BUFFER
2
ANALOG
FILTER
2
PGA
2
HYBRID
CIRCUIT
2
ANALOG
FILTER
2
DRIVER
2
2
TX_GAIN
TO
VCXO
T
X
R
X
3
AD6472
FEATURES
Integrated Front End for Single Pair or Two Pair HDSL
Systems
Meets ETSI Specifications
Supports 1168 Kbps and 2.32 Mbps
Transmit and Receive Signal Path Functions
Receive Hybrid Amplifier, PGA and ADC
Transmit DAC, Filter and Differential Outputs
Programmable Filters
Control and Ancillary Functions
Timing Recovery DAC
Normal Loopback and Low Power Modes
Simple Interface-to-Digital Transceivers
Single 5 V Power Supply
Power Consumption: 320 mW—(Excluding Driver)
Package: 80-Lead MQFP
Operating Temperature: –40
8
C to +85
8
C
GE NE RAL DE SCRIPT ION
T he AD6472 is a single chip analog front end for two pair or
single pair HDSL applications that use 1168 K bps or 2.32 Mbps
data rates.
T he AD6472 integrates all the transmit and receive functional
blocks together with the timing recovery DAC.
T he digital interface is designed to support industry standard
digital transceivers.
While providing the full analog front end for ET SI standards
(two pair or single pair HDSL applications) the AD6472 sup-
ports other applications because the architecture allows for
bypassing the functional blocks.
T he normal, low power, and loopback modes and the digital
interface combine to make the AD6472 simple to integrate into
systems.
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