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參數(shù)資料
| 型號： | AD647L |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Ultralow Drift, Dual BiFET Op Amp |
| 中文描述： | 超低漂移，雙BiFET運算放大器 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 150K |
| 代理商： | AD647L |
AD6472
–7–
T able VI. 40% to 60% Duty Cycle RX CLK Clock
when the RX CLK = 1160 kHz
Symbol
Parameter
Min
T yp
Max
Units
t
C
t
CH
t
CL
t
OD
Latency
Clock Period
Clock Pulsewidth High
Clock Pulsewidth Low
Output Delay
Pipeline Delay
862
ns
ns
ns
ns
Cycles
342
514
8
3
514
342
19
3
13
3
T able VII. 40% to 60% Duty Cycle RX CLK when the
RX CLK = 1160
3
2 kHz
Symbol
Parameter
Min
T yp
Max
Units
t
C
t
CH
t
CL
t
OD
Latency
Clock Period
Clock Pulsewidth High
Clock Pulsewidth Low
Output Delay
Pipeline Delay
431
ns
ns
ns
ns
Cycles
171
257
8
3
257
171
19
3
13
3
Receive Interface T iming
T he analog input is sampled at the rising edge of the RX CLK .
T he digital data, RX 11:RX 0, is valid on each falling edge of
RX CLK . Figure 4 shows a three-cycle latency on the receive
data.
T able V through T able VII lists the RX CLK clock switching
specifications for various RX CLK conditions. See T able IV,
Configuration Control.
T able V. 40% to 60% Duty Cycle when the RX CLK
= 1168
÷
2 kHz
Symbol
Parameter
Min
T yp
Max
Units
t
C
t
CH
t
CL
t
OD
Latency
Clock Period
Clock Pulsewidth High
Clock Pulsewidth Low
Output Delay
Pipeline Delay
1712
ns
ns
ns
ns
Cycles
685
1027
8
3
1027
685
19
3
13
3
t
C
t
CL
t
CH
t
OD
DATA1
S4
S3
S2
S1
ANALOG
INPUT
INPUT
CLOCK
RXCLK
OUTPUT
DATA
RX11:RX0
Figure 4. Receive Interface Timing Diagram
t
H
$
10ns
2
TX_CLK
TX_SYNC
TX_DATA
D11
MSB
D10
D9
D8
D7
D5
D6
D4
D3
D2
D1
D0
X
X
X
X
D11
MSB
D10
D9
1. THE RISING EDGE TO TX_SYNC CAN OCCUR ANYWHERE. TX_SYNC MUST BE AT LEAST ONE CLOCK CYCLE WIDE.
2. TX_SYNC FALLING EDGE MUST OCCUR AFTER THE TX_CLK RISING EDGE THAT CAPTURED THE SERIAL LSB.
THIS ENSURES CORRECT LOADING INTO THE DAC.
THE FIRST 12 BITS OF THE 16-BIT SERIAL WORD ARE THE INPUT TO THE TX PATH DAC, MSB FIRST. THE NUMBER
SYSTEM IS TWOS COMPLEMENT, AS FOLLOWS:
FULL SCALE
1/2 FULL SCALE
1/2 FULL SCALE
MINUS 1LSB
ZERO
OUTPUT
011111111111
000000000000
111111111111
WORD
100000000000
1
t
SU
$
12ns
Figure 5. Transmit Interface Timing Diagram
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