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AD6472
–4–
REV. 0
Pin
Mnemonic
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
+5 V_DVDD
DGND
MODE_SEL0
MODE_SEL1
AA_FLT R_BP
PWRDN
NC
T X _GAIN_SEL
T X _DRVR_BP
ADC_BUF_BP
T X _LPF_BP
T ST GND
LOOPBACK
DGND
+3 V_DVDD
T X _DAT A
T X _SYNC
T X _CLK
+5 V_DVDD
DGND
NC
IOUT _SET
+5 V Digital Supply.
Digital Ground.
Bit Rate—Filter Corner Select.
Bit Rate—Filter Corner Select.
Antialiasing Filter Bypass.
Power-Down Active Low.
No Connect.
T ransmit Attenuation (6 dB) Select.
T ransmit Driver Bypass.
ADC Buffer Bypass.
T ransmit Filter Bypass.
Factory test pin. Connect to DGND.
Loopback Select.
Digital Ground.
+3.3 V Digital Supply.
T ransmit Data Input.
T ransmit Data Frame Sync Input.
T ransmit Clock Input.
+5 V Digital Supply.
Digital Ground.
No Connect.
DAC Output Current Full Scale
(With Resistor to Ground).
No Connect.
Decoupling Pin for Internal Node.
Decoupling Pin for Internal Node.
T X DAC Complementary Current
Output.
T X DAC Complementary Current
Output.
Analog Ground.
+5 V Analog Supply.
Differential Input to LPF.
Differential Input to LPF.
Differential Output from T ransmit
(If Driver Bypassed).
Differential Output from T ransmit
(If Driver Bypassed).
+5 V Analog Supply.
Differential Driver Output.
Differential Driver Output.
Analog Ground.
Hybrid Noninverting Input.
Hybrid Noninverting Input.
Hybrid Inverting Input.
23
24
25
26
NC
CAP_B
CAP_C
T X _IOUT _A
27
T X _IOUT _B
28
29
30
31
32
AGND
AVDD
T X _LPF_IN_B
T X _LPF_IN_A
T X _LPF_OUT _B
33
T X _LPF_OUT _A
34
35
36
37
38
39
40
AVDD
DRVR_OUT _B
DRVR_OUT _A
AGND
HYB_IN2_B
HYB_IN2_A
HYB_IN1_B
PIN CONFIGURAT IONS
Pin
Mnemonic
Description
41
42
43
44
45
46
47
HYB_IN1_A
AGND
AVDD
PGA_GC2
PGA_GC1
PGA_GC0
AA_FLT R_OUT B Differential Output of the
Antialiasing Filter.
AA_FLT R_OUT A Differential Output of the
Antialiasing Filter.
ADC_INB
Differential Input to the ADC.
ADC_INA
Differential Input to the ADC.
REF_COM
Reference Common.
CAP_T OP
Decoupling Pin for ADC Reference.
CAP_BOT
Decoupling Pin for ADC Reference.
VREF
External Voltage Reference.
CM_LVL
Common-Mode Level.
(1/2 Supply Voltage, Nominally.)
AGND
Analog Ground.
AVDD
+5 V Analog Supply.
DGND
Digital Ground.
+5 V_ DVDD
+5 V Digital Supply.
NC
No Connect.
+3 V_ DVDD
+3 V Digital Supply.
T R_DAC_OUT
T iming Recovery DAC Output
Voltage.
SDAT A
Serial Data Input to T iming Recov-
ery DAC.
SFRAME
Frame Sync for T iming Recovery.
SCLK
Clock for T iming Recovery DAC.
Serial Data.
RX 0
Digital Output Data.
RX 1
Digital Output Data.
RX 2
Digital Output Data.
RX 3
Digital Output Data.
RX 4
Digital Output Data.
RX 5
Digital Output Data.
DGND
Digital Ground.
+3 V_DVDD
+3 V Digital Supply.
RX 6
Digital Output Data.
RX 7
Digital Output Data.
RX 8
Digital Output Data.
RX 9
Digital Output Data.
RX 10
Digital Output Data.
RX 11
Digital Output Data.
RX CLK
Clock Input for ADC Data.
Hybrid Inverting Input.
Analog Ground.
+5 V Analog Supply.
PGA Gain Select Bits.
PGA Gain Select Bits.
PGA Gain Select Bits.
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
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