參數(shù)資料
型號： AD6636PCB
廠商： Analog Devices, Inc.
元件分類： 數(shù)字上／下變頻
英文描述： 150 MSPS Wideband Digital Down-Converter (DDC)
中文描述： 150MSPS的寬帶數(shù)字下變頻器（DDC）
文件頁數(shù)： 36/72頁
文件大?。?/td> 1629K
代理商： AD6636PCB
AD6636
Programming CRCF Registers for an Asymmetrical Filter
To program the CRCF registers for an asymmetrical filter:
Rev. 0 | Page 36 of 72
1.
Write
NTAPS
– 1 in the CRCF taps register, where
NTAPS
is the number of filter taps. The absolute maximum value
for
NTAPS
is 64 in asymmetrical filter mode.
2.
Write 0 for the CRCF coefficient offset register.
3.
Write 0 for the symmetrical filter bit in the CRCF control
register.
4.
In the CRCF start address register, write the start address
for the coefficient RAM, typically equal to the coefficient
offset register.
5.
In the CRCF stop address register, write the stop address
for the coefficient RAM, typically equal to the following:
Coefficient Offset
+
NTAPS
– 1
6.
Write all coefficients in reverse order (start with last
coefficient) to the CRCF coefficient memory register. In
8-bit microport mode or serial port mode, write the lower
byte of the memory register first and then the higher byte.
In 16-bit microport mode, write the lower 16-bits of the
CRCF memory register first and then the high four bits.
After each write access to the CRCF coefficient memory
register, the internal RAM address is incremented starting
with the start address and ending with the stop address.
Note that each write or read access increments the internal
RAM address. Therefore, all coefficients should be read first
before reading them back. Also, for debugging purposes, each
RAM address can be written individually by making the start
and stop addresses the same. Therefore, to program one RAM
location, the user writes the address of the RAM location to
both the start and stop address registers, and then writes the
coefficient memory register.
Programming CRCF Registers for a Symmetrical Filter
To program the CRCF registers for a symmetrical filter:
1.
Write
NTAPS
– 1 in the CRCF taps register, where
NTAPS
is the number of filter taps. The absolute maximum value
for
NTAPS
is 128 in symmetrical filter mode.
2.
Write
ceil
(64 –
NTAPS
/2) for the CRCF coefficient offset
register, where the ceil function takes the closest integer
greater than or equal to the argument.
3.
Write 1 for the symmetrical filter bit in the CRCF control
register.
4.
In the CRCF start address register, write the start address
for the coefficient RAM, typically equal to the coefficient
offset register.
5.
In the CRCF stop address register, write the stop
address for the coefficient RAM, typically equal to
ceil
(
NTAPS
/2) – 1.
6.
Write all coefficients to the CRCF coefficient memory
register, starting with middle of the filter and working
towards the end of the filter. When coefficients are
numbered 0 to
NTAPS
– 1, the middle coefficient is given
by the coefficient number
ceil
(
NTAPS
/2). In 8-bit
microport mode or serial port mode, write the lower byte
of the memory register first and then the higher byte. In
16-bit microport mode, write the lower 16-bits of the
CRCF memory register first and then the high four bits.
After each write access to the CRCF coefficient memory
register, the internal RAM address is incremented starting
with the start address and ending with the stop address.
Note that each write or read access increments the internal
RAM address. Therefore, all coefficients should be read first
before reading them back. Also, for debugging purposes, each
RAM address can be written individually by making the start
and stop addresses the same. Therefore, to program one RAM
location, the user writes the address of the RAM location to
both the start and stop address registers, and then writes the
coefficient memory register.
INTERPOLATING HALF-BAND FILTER
The AD6636 has interpolating half-band FIR filters that
immediately follow the CRCF programmable FIR filters and
precede the second data router. Each interpolating half-band
filter takes 22-bit I and 22-bit Q data from the preceding CRCF
and outputs rounded 22-bit I and 22-bit Q data to the second
data router. A 10-tap fixed-coefficient filter is implemented in
this stage.
The maximum input rate into this block is 17 MHz. Conse-
quently, the maximum output is constrained to 34 MHz. The
normalized coefficients used in the implementation and the
10-bit decimal equivalent value of the coefficients are listed in
Table 21. Other coefficients are 0.
Table 21. Interpolating HB Filter Fixed Coefficients
Coefficient
Number
Coefficient
C1, C11
0.02734375
C3, C9
0.12890625
C5, C7
0.603515625
C6
1
Normalized
Decimal Coefficient
(10-Bit)
14
66
309
512
The half-band filters interpolate the incoming data by 2×. For a
channel running at 2× the chip rate, the half-band can be used
to output channel data at 4× the chip rate. The interpolation
operation creates an image of the baseband signal, which is
filtered out by the half-band filter.
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