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參數(shù)資料
| 型號(hào)： | AD6644 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14-Bit, 40 MSPS/65 MSPS A/D Converter |
| 中文描述： | 14位，40 MSPS/65 MSPS的A / D轉(zhuǎn)換 |
| 文件頁(yè)數(shù)： | 7/19頁(yè) |
| 文件大?。?/td> | 1155K |
| 代理商： | AD6644 |
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AD6644
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7
–
REV. 0
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Resistance, Differential Analog Input
Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capaci-
tance and differential input impedances are measured with a
network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to the
converter to generate a full-scale response. Peak differential voltage
is computed by observing the voltage on a single pin and sub-
tracting the voltage from the other pin, which is 180 degrees out
of phase. Peak-to-peak differential is computed by rotating the
inputs phase 180 degrees and taking the peak measurement again.
The difference is then computed between both peak measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic 1 state to achieve rated
performance; pulsewidth low is the minimum time ENCODE
pulse should be left in low state. See timing implications of
changing t
ENCH
in text. At a given clock rate, these specs define
an acceptable ENCODE duty cycle.
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
Power
V
0 001
.
Full Scale
Full Scalerms
|Z
Input
=
10
2
log
Harmonic Distortion, 2nd
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, 3rd
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a
“
best straight line
”
determined by a least-square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE
and the time when all output data bits are within
valid logic levels.
Noise (For Any Range Within the ADC)
V
NOISE
FS
Signal
10
dBm
dBFS
=
×
|Z
.
–
0 001 10
Where
Z
is the input impedance,
FS
is the full scale of the device
for the frequency in question,
SNR
is the value for the particular
input level and
Signal
is the signal level within the ADC reported
in dB below full scale. This value includes both thermal and
quantization noise.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in power
supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics, but excluding dc.
Signal-to-Noise Ratio (Without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full scale)
to the rms value of the sum of all other spectral components,
excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the peak
spurious spectral component. The peak spurious component may
or may not be a harmonic. May be reported in dBc (i.e., degrades
as signal level is lowered), or dBFS (always related back to con-
verter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the worst
spurious component (excluding the 2nd and 3rd harmonic)
reported in dBc.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD6644PCB | 14-Bit, 40 MSPS/65 MSPS A/D Converter |
| AD6644ST | 14-Bit, 40 MSPS/65 MSPS A/D Converter |
| AD6644AST-40 | 14-Bit, 40 MSPS/65 MSPS A/D Converter |
| AD6644AST-65 | 14-Bit, 40 MSPS/65 MSPS A/D Converter |
| AD6645 | 14-Bit, 80 MSPS A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6644AST-40 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 40Msps 14-bit Parallel 52-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:14 BIT 40 MSPS ADC - Bulk 制造商:Analog Devices 功能描述:CONNECTOR 14 BIT |
| AD6644AST-65 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 65Msps 14-bit Parallel 52-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:14 BIT 65 MSPS ADC - Bulk 制造商:Analog Devices 功能描述:A/D Converter (A-D) IC |
| AD6644ASTZ-40 | 功能描述:IC ADC 14BIT 40MSPS CMOS 52-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD6644ASTZ-40 | 制造商:Analog Devices 功能描述:IC 14-BIT ADC |
| AD6644ASTZ-65 | 功能描述:IC ADC 14BIT 65MSPS CMOS 52-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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