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參數(shù)資料
| 型號： | AD6645PCB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14-Bit, 80 MSPS A/D Converter |
| 中文描述： | 14位，80 MSPS的A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大小： | 2230K |
| 代理商： | AD6645PCB |
REV. 0
–15–
AD6645
AD6645
AIN
AIN
V
REF
AD8138
V
OCM
5V
499
499
499
499
25
25
C
F
V
IN
C
F
DIGITAL
OUTPUTS
Figure 11. DC-Coupled Analog Input Circuit
Power Supplies
Care should be taken when selecting a power source. The use of
linear dc supplies with rise-times of <45 ms is highly recom-
mended. Switching supplies tend to have radiated components
that may be
“
received
”
by the AD6645. Each of the power
supply pins should be decoupled as closely to the package as
possible using 0.1
m
F chip capacitors.
The AD6645 has separate digital and analog power supply pins.
The analog supplies are denoted AV
CC
and the digital supply
pins are denoted DV
CC
. Although analog and digital supplies
may be tied together, best performance is achieved when the
supplies are separate. This is because the fast digital output
swings can couple switching current back into the analog supplies.
Note that AV
CC
must be held within 5% of 5 V. The AD6645 is
specified for DV
CC
= 3.3 V as this is a common supply for
digital ASICS.
Digital Outputs
Care must be taken when designing the data receivers for the AD6645.
It is recommended that the digital outputs drive a series resistor
followed by a gate such as the 74LCX574. To minimize capaci-
tive loading, there should only be one gate on each output pin.
An example of this is shown in the evaluation board schematic
shown in Figure 13. The digital outputs of the AD6645 have a
constant output slew rate of 1 V/ns. A typical CMOS gate combined
with a PCB trace will have a load of approximately 10 pF. There-
fore, as each bit switches 10 mA
10
dynamic current per bit will flow in or out of the device. A full-
scale transition can cause up to 140 mA (14 bits
￥
10 mA/bit) of
current to flow through the output stages. The series resistors
should be placed as close to the AD6645 as possible to limit the
amount of current that can flow into the output stage. These
switching currents are confined between ground and the DV
CC
pin. Standard TTL gates should be avoided since they can appre-
ciably add to the dynamic switching currents of the AD6645. It
should be noted that extra capacitive loading will increase out-
put timing and invalidate timing specifications. Digital output
timing is guaranteed for output loads up to 10 pF.
Digital output states for given analog input levels are shown in Table I.
1
1
pF
V
ns
￥
∏
of
Grounding
For optimum performance, it is highly recommended that a com-
mon ground be utilized between the analog and digital power
planes. The primary concern with splitting grounds is that dynamic
currents may be forced to travel significant distances in the sys-
tem before recombining back at the common source ground. This
can result in a large and undesirable ground loop. The most
common place for this to occur is on the digital outputs of the
ADC. Ground loops can contribute to digital noise being coupled
back onto the ADC front end. This can manifest itself as either
harmonic spurs, or very high order spurious products that can
cause excessive spikes on the noise floor. This noise coupling is
less likely to occur at lower clock speeds since the digital noise has
more time to settle between samples. In general, splitting the
analog and digital grounds can frequently contribute to undesir-
able EMI-RFI and should therefore be avoided.
Conversely, if not properly implemented, common grounding can
actually impose additional noise issues since the digital ground
currents are riding on top of the analog ground currents in close
proximity to the ADC input. To minimize the potential for
noise coupling further, it is highly recommended that multiple
ground return traces/vias be placed such that the digital output
currents do not flow back towards the analog front end, but are
routed quickly away from the ADC. This does not require a
split in the ground plane and can be accomplished by simply
placing substantial ground connections directly back to the
supply at a point between the analog front end and the digital
outputs. The judicious use of ceramic chip capacitors between
the power supply and ground planes will also help suppress
digital noise. The layout should incorporate enough bulk capacitance
to supply the peak current requirements during switching periods.
Layout Information
The schematic of the evaluation board (Figure 13) represents a
typical implementation of the AD6645. A multilayer board is
recommended to achieve best results. It is highly recommended
that high quality, ceramic chip capacitors be used to decouple
each supply pin to ground directly at the device. The pinout of
the AD6645 facilitates ease of use in the implementation of
high-frequency, high-resolution design practices. All of the digital
outputs are segregated to two sides of the chip, with the inputs on
the opposite side for isolation purposes.
Care should be taken when routing the digital output traces. To
prevent coupling through the digital outputs into the analog
portion of the AD6645, minimal capacitive loading should be
placed on these outputs. It is recommended that a fan-out of
only one gate should be used for all AD6645 digital outputs.
The layout of the encode circuit is equally critical. Any noise
received on this circuitry will result in corruption in the digitiza-
tion process and lower overall performance. The encode clock
must be isolated from the digital outputs and the analog inputs.
Table I. Two’s Complement Output Coding
AIN
Level
AIN
Level
Output
State
Output
Code
V
REF
+ 0.55 V
V
REF
V
REF
–
0.55 V
V
REF
–
0.55 V
V
REF
V
REF
+ 0.55 V
Positive FS
Midscale
Negative FS
01 1111 1111 1111
00
…
0/11
…
1
10 0000 0000 0000
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