參數(shù)資料
型號(hào)： AD664BD-UNI
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： Monolithic 12-Bit Quad DAC
中文描述： QUAD, PARALLEL, WORD INPUT LOADING, 10 us SETTLING TIME, 12-BIT DAC, CDIP28
封裝： HERMETIC SEALED, CERAMIC, DIP-28
文件頁(yè)數(shù)： 3/20頁(yè)
文件大?。?/td> 566K
代理商： AD664BD-UNI
AD664
Model
JN/JP/AD/AJ/SD
Typ
KN/KP/BD/BJ/BE/TD/TE
Min
Typ
Min
Max
Max
Units
DIGITAL INPUTS
V
IH
V
IL
Data Inputs
I
IH
@ V
IN
= V
LL
I
IL
@ V
IN
= DGND
CS
/DS0/DS1/
RST
/
RD
/
LS
I
IH
@ V
IN
= V
LL
I
IL
@ V
IN
= V
LL
MS
/
TR
12
I
IH
@ V
IN
= V
LL
I
IL
@ V
IN
= DGND
QS0
/
QSl
/
QS2
l2
I
IH
@ V
IN
= V
LL
I
IL
@ V
IN
= DGND
2.0
0
*
*
Volts
Volts
0.8
*
–10
–10
±
1
±
1
10
10
*
*
*
*
*
*
μ
A
μ
A
–10
–10
±
1
±
1
10
10
*
*
*
*
*
*
μ
A
μ
A
–10
–10
5
–5
10
0
*
*
*
*
*
*
μ
A
μ
A
–10
–10
5
±
1
10
10
*
*
*
*
*
*
μ
A
μ
A
DIGITAL OUTPUTS
V
OL
@ 1.6 mA Sink
V
OH
@ 0.5 mA Source
0.4
*
Volts
Volts
2.4
*
TEMPERATURE RANGE
JN/JP/KN/KP
AD/AJ/BD/BJ/BE
SD/TD/TE
0
–40
–55
+70
+85
+125
*
*
*
*
*
*
°
C
°
C
°
C
NOTES
1
A minimum power supply of
±
12.0 V is required for 0 V to +10 V and
±
10 V operation. A minimum power supply of
±
11.4 V is required for –5 V to +5 V operation.
2
For V
CC
< +12 V and V
EE
> –12 V. Voltage not to exeeed 10 V maximum.
3
Bipolar zero error is the difference from the ideal output (0 volts) and the actual output voltage with code 100 000 000 000 applied to the inputs.
4
Linearity error is defined as the maximum deviation of the actual DAC output from the ideal output (a straight line drawn from 0 to F.S. – 1 LSB).
5
FSR means Full-Scale Range and is 20 V for
±
10 V range and 10 V for
±
5 V range.
6
A minimum power supply of
±
12.0 V is required for a 10 V reference voltage.
7
Analog Ground Current is input code dependent.
8
Gain error matching is the largest difference in gain error between any two DACs in one package.
9
Offset error matching is the largest difference in offset error between any two DACs in one package.
10
Bipolar zero error matching is the largest difference in bipolar zero error between any two DACs in one package.
11
Linearity error matching is the difference in the worst ease linearity error between any two DACs in one package.
12
44-pin versions only.
*Specifications same as JN/JP/AD/AJ/SD.
Specifications subject to change without notice.
Specifications shown in
boldface
are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
ABSOLUTE MAXIMUM RATINGS*
V
LL
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +7 V
V
CC
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V
V
EE
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 V to 0 V
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300
°
C, 10 sec
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –1 V to +1 V
Reference Input . . . . . . . . . . . . . . . . . . V
REF
≤
±
10 V and V
REF
≤
(V
CC
– 2 V, V
EE
+ 2 V)
V
CC
to V
EE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +36 V
CAUTION
ESD (electrostatic discharge) sensitive device. Unused devices must be stored in conductive foam
or shunts. The protective foam should be discharged to the destination socket before devices are
removed.
WARNING!
ESD SENSITIVE DEVICE
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Outputs . . . . . . . . . . . . . . . . . . . . . Indefinite Shorts to
V
CC,
V
LL
, V
EE
and GND
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
REV. C
–3–
相關(guān)PDF資料
PDF描述
AD664JN-BIP Monolithic 12-Bit Quad DAC
AD664JN-UNI Monolithic 12-Bit Quad DAC
AD664JP Monolithic 12-Bit Quad DAC
AD664TD-BIP Monolithic 12-Bit Quad DAC
AD664TD-UNI Monolithic 12-Bit Quad DAC
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