參數(shù)資料
型號(hào)： AD6655-150EBZ1
廠商： Analog Devices, Inc.
英文描述： IF Diversity Receiver
中文描述： IF分集接收機(jī)
文件頁(yè)數(shù)： 52/84頁(yè)
文件大?。?/td> 2012K
代理商： AD6655-150EBZ1
AD6655
Rev. 0 | Page 52 of 84
Addr.
(Hex)
0x0D
Register
Name
Test Mode
(Local)
Bit 7
(MSB)
Open
Bit 6
Open
Bit 5
Reset
PN long
sequence
Bit 4
Reset
PN short
sequence
Bit 3
Open
Bit 2
Bit 1
Output test mode
000 = off (default)
001 = midscale short
010 = positive FS
011 = negative FS
100 = alternating
checkerboard
101 = PN long sequence
110 = PN short sequence
111 = one/zero word
toggle
Bit 0
(LSB)
Default
Value
(Hex)
0x00
Default
Notes/
Comments
When
enabled, the
test data is
placed on the
output pins
in place of
ADC output
data
0x10
Offset Adjust
(Local)
Output Mode
Open
Open
Offset adjust in LSBs from +31 to -32 (twos complement format)
0x00
0x14
Drive
strength
0 V to 3.3
V CMOS or
ANSI
LVDS;
1 V to 1.8
V CMOS or
reduced
LVDS
(global)
Invert
DCO clock
Output
type
0 = CMOS
1 = LVDS
(global)
Interleaved
CMOS
(global)
Output
enable
bar (local)
Open
Output
invert
(local)
00 = offset binary
01 = twos complement
01 = gray code
11 = offset binary
(local)
0x00
Configures
the outputs
and the
format of
the data
0x16
Clock Phase
Control
(Global)
Open
Open
Open
Open
Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
DCO clock delay
(delay = 2500 ps × register value/31)
00000 = 0 ps
00001 = 81 ps
00010 = 161 ps
…
11110 = 2419 ps
11111 = 2500 ps
Open
Open
0x00
Allows
selection of
clock delays
into the input
divider
0x17
DCO Output
Delay
(Global)
Open
Open
Open
0x00
0x18
VREF Select
(Global)
Reference voltage
selection
00 = 1.25 V p-p
01 = 1.5 V p-p
10 = 1.75 V p-p
11 = 2.0 V p-p
(default)
Open
Open
Open
Open
0xC0
Digital Feature Control Registers
0x100
Sync Control
(Global)
Signal
monitor
sync
enable
Half-band
next sync
only
Half-band
sync
enable
NCO32
next sync
only
NCO32
sync
enable
Clock
divider
next
sync
only
Open
Clock
divider
sync
enable
Master sync
enable
0x00
0x101
f
S
/8 Output
Mix Control
(Global)
FIR Filter and
Output Mode
Control
(Global)
Open
Open
f
S
/8 start state
Open
f
S
/8 next
sync only
f
S
/8 sync
enable
0x00
0x102
Open
Open
Open
Open
FIR gain
0 = gain of
2
1 = gain of
1
Half-band
decimation
phase
f
S
/8
output
mix
disable
Complex
output
enable
FIR filter
enable
0x00
0x103
Digital Filter
Control
(Global)
Open
Open
Open
Open
Spectral
reversal
High-pass/
low-pass
select
Open
0x01
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