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參數資料
| 型號： | AD668A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit Ultrahigh Speed Multiplying D/A Converter |
| 中文描述： | 12位超高速乘法D / A轉換器 |
| 文件頁數： | 6/16頁 |
| 文件大?。?/td> | 602K |
| 代理商： | AD668A |
AD668
REV. A
–6–
0.1
<
V
IN
V
NOM
<
1.2
0 <
V
IN
/V
NOM
< 0.1 constitutes an undervoltage condition and
is subject to the specified recovery time.
1.2 < V
IN
/V
NOM
constitutes an overvoltage condition. This can
saturate the DAC transistors, resulting in decreased response
time and can, over extended time, damage the part through ex-
cessive power dissipation. Figure 3 indicates the specified re-
gions of operation in both the unipolar and bipolar cases.
The small signal 3 dB bandwidth of the V
IN
channel is 15 MHz.
The large signal 3 dB bandwidth is approximately 10 MHz.
V
OUT
is limited by the specified output compliance: –2 V to
+1.2 V.
Figure 3. Quadrant Plots of the AD668
CIRCUIT DESCRIPTION OF THE AD668
Successful design of high speed, high resolution systems de-
mands a designer’s solid working knowledge of the components
being used. The AD668 has been carefully configured to pro-
vide maximum functionality in a variety of applications. While it
is beyond the scope of this data sheet to exhaustively cover each
potential application topology, the detailed information that
follows is intended to provide the designer with a sufficiently
thorough understanding of the part’s inner workings to allow
selection of the circuit topology to best suit the application.
CURRENT OUTPUT VS. VOLTAGE-OUTPUT
As indicated in the FUNCTIONAL DESCRIPTION, the
AD668 output may be taken as either a voltage or a current,
depending on external circuit connections. In the current output
mode, the DAC output (Pin 20) is tied to a summing junction,
and the current flowing from the DAC into this summing junc-
tion is sensed. In this mode, the DAC output scale is insensitive
to whether the load resistor, R
LOAD
, is shorted (Pin 19 con-
nected to Pin 20), or grounded (Pin 19 connected to Pin 18).
However, the connection of this resistor does affect the output
impedance of the DAC and may have a significant impact on
the noise gain and stability of the external circuitry. Grounding
R
LOAD
will reduce the output impedance, thereby increasing the
noise gain and also enhancing the stability of a circuit using a
non-unity-gain-stable op amp (see Figure 10).
In the voltage output mode, the DAC’s output current flows
through its own internal impedance (perhaps in parallel with an
external impedance) to generate a voltage. In this case, the DAC
output scale is directly dependent on the load impedance. The
temperature coefficient of the AD668’s transfer function will be
lowest when used in the voltage output mode.
OUTPUT VOLTAGE COMPLIANCE
The AD668 has an output compliance range of –2.0 V to
+1.2 V (with respect to the LCOM pin). The current steering
output stages will be unaffected by changes in the output termi-
nal voltage over this range. However, as shown in Figure 4,
there is an equivalent output impedance of 200
in parallel
with 15 pF at the output terminal, producing an equivalent er-
ror current if the voltage deviates from the ladder common.
This is a linear effect which does not change with input code.
Operation beyond the maximum compliance limits may cause
either output stage saturation or breakdown, resulting in non-
linear performance. The positive compliance limit is not af-
fected by the positive power supply, but is a function of the
output current and the logic threshold voltage at V
TH
, Pin 13.
Figure 4. Equivalent Output Circuit
ANALOG INPUT CONSIDERATIONS
The reference input buffer can be viewed as a resistive divider
connected to one terminal of an op amp, as shown in Figure 5.
A unit DAC current source drives a resistor to produce a voltage
that is fed back to the opposite terminal of the op amp. Resistor
R
FEEDBACK
is laser-trimmed to ensure that a 1 V input to node A of
the op amp will produce a 10.24 mA DAC output. REFIN1 and
REFIN2 may be configured in any way the user chooses to pro-
vide a nominal input full scale of 1 V at node A. R1 and R2 are
sized and trimmed to provide both a 5:1 voltage divider and a
parallel impedance that matches the impedance at node B,
thereby reducing the amplifier offset voltage due to bias current.
The resistive divider is trimmed with an external 50
resistor in
series with the 4k leg (R2). This provides a gain trim range of
±
1%
using a 100
trim potentiometer (Figure 7). If trimming is not
desired, a 50
resistor may be used in place of the potentiom-
eter to produce the specified gain accuracy, or the resistor may
be omitted altogether to produce a nominal gain error of +1%.
Figure 5. Equivalent Analog Input Circuitry
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| AD668AQ | 12-Bit Ultrahigh Speed Multiplying D/A Converter |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD668AQ | 制造商:Rochester Electronics LLC 功能描述:IC,MONO 12-BIT MULTI D/A - Bulk |
| AD668J | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit Ultrahigh Speed Multiplying D/A Converter |
| AD668JQ | 制造商:Analog Devices 功能描述:DAC 1-CH R-2R/Current Steering 12-bit 24-Pin CDIP Tube |
| AD668K | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit Ultrahigh Speed Multiplying D/A Converter |
| AD668KQ | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
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