參數(shù)資料
型號： AD678AJ
廠商： Analog Devices Inc
文件頁數(shù)： 11/14頁
文件大?。?/td> 0K
描述： IC ADC 12BIT 200KSPS 44-JLCC
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 200k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 745mW
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-JLCC（16.39x16.39）
包裝： 管件
輸入數(shù)目和類型： 1 個單端，單極；1 個單端，雙極
AD678
REV. C
–6–
PIN DESCRIPTION
28-Lead DIP 44-Lead
Symbol
Pin No.
JLCC Pin No. Type
Name and Function
AGND
7
11
P
Analog Ground. This is the ground return for AIN only.
AIN
6
10
AI
Analog Signal Input.
BIPOFF
10
15
AI
Bipolar Offset. Connect to AGND for +10 V input unipolar mode and straight binary
output coding. Connect to REFOUT through 50
resistor for ±5 V input bipolar mode
and twos complement binary output coding. See Figures 7 and 8.
CS
4
6
DI
Chip Select. Active LOW.
DGND
14
23
P
Digital Ground
DB11–DB4
26–19
40, 39, 37, 36,
DO
Data Bits 11 through 4. In 12-bit format (see 12/
8 pin), these pins provide the upper 8 bits
35, 34, 33, 31
of data. In 8-bit format, these pins provide all 12 bits in two bytes (see R/
L pin).
Active HIGH.
DB3, DB2
18, 17
30, 27
DO
Data Bits 3 and 2. In 12-bit format, these pins provide Data Bit 3 and Data Bit 2.
Active HIGH. In 8-bit format they are undefined and should be tied to VDD.
DB1 (R/
L)
16
26
DO
In 12-bit format, Data Bit 1. Active HIGH.
DB0 (
HBE)
15
25
DO
In 12-bit format, Data Bit 0. Active HIGH.
EOC
27
42
DO
End-of-Convert. EOC goes LOW when a conversion starts and goes HIGH when the
conversion is finished. In asynchronous mode, EOC is an open drain output and
requires an external 3 k
pull-up resistor. See EOCEN and SYNC pins for information
on EOC gating.
EOCEN
1
DI
End-Of-Convert Enable. Enables EOC pin. Active LOW.
HBE (DB0)
15
25
DI
In 8-bit format, High Byte Enable. If LOW, output contains high byte. If HIGH, output
contains low byte.
OE
2
3
DI
Output Enable. The falling edge of
OE enables DB11–DB0 in 12-bit format and
DB11–DB4 in 8-bit format. Gated with
CS. Active LOW.
REFIN
9
14
AI
Reference Input. +5 V input gives 10 V full-scale range.
REFOUT
8
12
AO
+5 V Reference Output. Tied to REFIN through 50
resistor for normal operation.
R/
L (DB1)
16
26
DI
In 8-bit format, Right/Left justified. Sets alignment of 12-bit result within 16-bit field.
Tied to VDD for right-justified output and tied to DGND for left-justified output.
SC
3
5
DI
Start Convert. Active LOW. See SYNC pin for gating.
SYNC
13
21
DI
SYNC Control. If tied to VDD (synchronous mode), SC, EOC and EOCEN are gated
by
CS. If tied to DGND (asynchronous mode), SC and EOCEN are independent of CS,
and EOC is an open drain output. EOC requires an external 3 k
pull-up resistor in
asynchronous mode.
VCC
11
17
P
+12 V Analog Power.
VEE
5
8
P
–12 V Analog Power.
VDD
28
43
P
+5 V Digital Power.
12/
8
12
19
DI
Twelve/eight-bit format. If tied HIGH, sets output format to 12-bit parallel. If tied
LOW, sets output format to 8-bit multiplexed.
No Connect
2, 4, 7, 9, 13,
These pins are unused and should be connected to DGND or VDD.
16, 18, 20, 22,
24, 28, 29, 32,
38, 41, 44
Type: AI = Analog Input; AO = Analog Output; DI = Digital Input (TTL and 5 V CMOS compatible); DO = Digital Output (TTL and 5 V CMOS compatible).
All DO pins are three-state drivers; P = Power.
PIN CONFIGURATIONS
DIP PACKAGE
JLCC PACKAGE
EOCEN
OE
VEE
AIN
AGND
SC
CS
REFOUT
REFIN
BIPOFF
VCC
12/
8
SYNC
DGND
13
18
1
2
28
27
5
6
7
24
23
22
3
4
26
25
8
21
920
10
19
11
12
17
16
14
15
TOP VIEW
(Not to Scale)
AD678
VDD
EOC
DB9
DB8
DB7
DB11
DB10
DB6
DB5
DB4
DB3
DB2
DB1 (R/
L)
DB0 (
HBE)
6
5
4
3
2
44 43 42 41 40
18 19 20 21 22
24 25 26 27 28
23
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
PIN 1
IDENTIFIER
TOP VIEW
NC
VEE
AIN
AGND
REFOUT
REFIN
BIPOFF
VCC
NC
DB9
DB8
DB7
DB10
DB6
DB5
DB4
DB3
CS
SC
NC
OE
NC
EOCEN
V
DD
EOC
DB11
NC
DGND
NC
12/
8
SYNC
DB0
(
HBE
)
DB1
(R/
L
)
DB2
NC
AD678
NC = NO CONNECT
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