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參數(shù)資料
| 型號(hào)： | AD678AJ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 3/14頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 200KSPS 44-JLCC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 745mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-JLCC（16.39x16.39） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極；1 個(gè)單端，雙極 |
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AD678
REV. C
–11–
The AD678 incorporates several features to help the user’s
layout. Analog pins (VEE) AIN, AGND, REFOUT, REFIN,
BIPOFF, VCC) are adjacent to help isolate analog from digital
signals. In addition, the 10 M
input impedance of AIN mini-
mizes input trace impedance errors. Finally, ground currents
have been minimized by careful circuit design. Current through
AGND is 200
A, with no code-dependent variation. The cur-
rent through DGND is dominated by the return current for
DB11–DB0 and EOC.
SUPPLY DECOUPLING
The AD678 power supplies should be well filtered, well regulated,
and free from high-frequency noise. Switching power supplies
are not recommended. These supplies generate spikes which can
induce noise in the analog system.
Decoupling capacitors should be located as close as possible to
all power supply pins. A 10
F tantalum capacitor in parallel
with a 0.1
F ceramic provides adequate decoupling. The power
supply pins should be decoupled directly to AGND.
An effort should be made to minimize the trace length between
the capacitor leads and the respective converter power supply
and common pins. The circuit layout should attempt to locate
the AD678, associated analog input circuitry and interconnec-
tions as far as possible from logic circuitry. A solid analog ground
plane around the AD678 will isolate large switching ground
currents. For these reasons, the use of wire wrap circuit con-
struction is not recommended; careful printed circuit construction
is preferred.
GROUNDING
If a single AD678 is used with separate analog and digital
ground planes, connect the analog ground plane to AGND and
the digital ground plane to DGND keeping lead lengths as short
as possible. Then connect AGND and DGND together at the
AD678. If multiple AD678s are used or the AD678 shares ana-
log supplies with other components, connect the analog and
digital returns together once at the power supplies rather than at
each chip. This prevents large ground loops which inductively
couple noise and allow digital currents to flow through the ana-
log system.
INTERFACING THE AD678 TO MICROPROCESSORS
The I/O capabilities of the AD678 allow direct interfacing to
general purpose and DSP microprocessor buses. The asynchro-
nous conversion control feature allows complete flexibility and
control with minimal external hardware.
The following examples illustrate typical AD678 interface
configurations.
A single-pass calibration can be done by substituting a bipolar
offset trim (error at minus full scale) for the bipolar zero trim
(error at midscale), using the same circuit. First, apply a signal
1/2 LSB above minus full scale (–4.9988 V for a
±5 V range)
and adjust R1 until the minus full-scale transition is located
(1000 0000 0000 to 1000 0000 0001). Then perform the gain
error trim as outlined above.
Figure 12. Unipolar Input Connections with Gain and
Offset Trims
Figure 13. Bipolar Input Connections with Gain and Offset
Trims
BOARD LAYOUT
Designing with high-resolution data converters requires careful
attention to layout. Trace impedance is a significant issue. At the
12-bit level, a 5 mA current through a 0.5
trace will develop a
voltage drop of 2.5 mV, which is 1 LSB for a 10 V full-scale span.
In addition to ground drops, inductive and capacitive coupling
need to be considered, especially when high- accuracy analog
signals share the same board with digital signals. Finally, power
supplies need to be decoupled in order to filter out ac noise.
Analog and digital signals should not share a common path.
Each signal should have an appropriate analog or digital return
routed close to it. Using this approach, signal loops enclose a
small area, minimizing the inductive coupling of noise. Wide PC
tracks, large gauge wire, and ground planes are highly recom-
mended to provide low impedance signal paths. Separate analog
and digital ground planes are also desirable, with a single inter-
connection point to minimize ground loops. Analog signals should
be routed as far as possible from digital signals and should cross
them at right angles.
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| AD678JD | 功能描述:IC ADC 12BIT SAMPLING 28-CDIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個(gè)單端，單極 |
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