參數(shù)資料
型號(hào)： AD679JN
廠商： Analog Devices Inc
文件頁數(shù)： 13/16頁
文件大?。?/td> 0K
描述： IC ADC 14BIT 128KSPS 28-DIP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
采樣率（每秒）： 128k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 745mW
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： 0°C ~ 70°C
安裝類型： 通孔
封裝/外殼： 28-DIP（0.600"，15.24mm）
供應(yīng)商設(shè)備封裝： 28-PDIP
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)單端，單極；1 個(gè)單端，雙極
AD679
REV. D
–6–
PIN FUNCTION DESCRIPTIONS
28-Lead
44-Lead
DIP
JLCC
Mnemonic Pin No.
Pin No.
Type
Name and Function
AGND
7
11
P
Analog Ground. This is the ground return for AIN only.
AIN
6
10
AI
Analog Signal Input.
BIPOFF
10
15
AI
Bipolar Offset. Connect to AGND for +10 V input unipolar mode and straight
binary output coding. Connect to REFOUT for
5 V input bipolar mode and
twos complement binary output coding.
CS
46
DI
Chip Select. Active LOW.
DGND
12, 14
23
P
Digital Ground.
DB7–DB0
26–19
40, 39, 37, 36,
DO
Data Bits. These pins provide all 14 bits in two bytes (8 + 6 bits). Active HIGH.
35, 34, 33, 31
EOC
27
42
DO
End-of-Convert. EOC goes LOW when a conversion starts and goes HIGH
when the conversion finishes. In asynchronous mode, EOC is an open-drain
output and requires an external 3 k
pull-up resistor. See EOCEN and SYNC
pins for information on EOC gating.
EOCEN
11
DI
End-of-Convert Enable. Enables EOC pin. Active LOW.
HBE
15
25
DI
High Byte Enable. If LOW, output contains high byte. If HIGH, output
contains low byte (corresponding to the most recently read high byte).
OE
23
DI
Output Enable. A down-going transition on
OE enables DB7 to DB0. Gated
with
CS. Active LOW.
REFIN
914AIReference Input. 5 V input gives 10 V full-scale range.
REFOUT
812AO5 V Reference Output. Tied to REFIN for normal operation.
SC
35
DI
Start Convert. Active LOW. See SYNC pin for gating.
SYNC
13
21
DI
SYNC Control. If tied to VDD (synchronous mode), SC and EOCEN are gated
by
CS. If tied to DGND (asynchronous mode), SC and EOCEN are indepen-
dent of
CS, and EOC is an open-drain output. EOC requires an external 3 k
pull-up resistor in asynchronous mode.
VCC
11
17
P
12 V Analog Power.
VEE
58
P
–12 V Analog Power.
VDD
28
43
P
5 V Digital Power.
—16U
Tie to DGND.
—
17–18
2, 4, 7, 9, 13,
U
These pins are unused and should be connected to DGND or VDD.
16, 18, 19, 20,
22, 24, 26, 27,
28, 29, 30, 32,
38, 41, 44
Type: AI = Analog Input. AO = Analog Output. DI = Digital Input (TTL and 5 V CMOS compatible). DO = Digital Output (TTL and 5 V CMOS compatible).
All DO pins are three-state drivers. P = Power. U = Unused.
DIP Package
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD679
DGND
SYNC
DGND
VCC
BIPOFF
REFIN
REFOUT
EOCEN
OE
SC
CS
AGND
AIN
VEE
HBE
DGND
DB0
DB1
DB2
VDD
EOC
DB7
DB6
DB3
DB4
DB5
PIN CONFIGURATIONS
JLCC Package
NC
AGND
REFOUT
NC
REFIN
BIPOFF
NC
VEE
AIN
NC
VCC
18 19 20 21 22 23 24 25 26 27 28
7
11
10
9
8
12
16
15
14
13
17
39
35
36
37
38
34
30
31
32
33
29
DB6
NC
DB5
DB4
DB3
DB2
DB1
NC
DB0
NC
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AD679
CS
SC
NC
OE
NC
EOCE
N
V
DD
EOC
NC
DB7
NC
SYNC
NC
DGND
HBE
NC
65
4
3
21
44 43 42 41 40
NC = NO CONNECT
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