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參數資料
| 型號： | AD712KRZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 3/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP BIFET DUAL PREC 8SOIC |
| 標準包裝： | 750 |
| 放大器類型： | J-FET |
| 電路數： | 2 |
| 轉換速率： | 20 V/µs |
| -3db帶寬： | 4MHz |
| 電流 - 輸入偏壓： | 20pA |
| 電壓 - 輸入偏移： | 200µV |
| 電流 - 電源： | 5mA |
| 電流 - 輸出 / 通道： | 25mA |
| 電壓 - 電源，單路/雙路(±)： | 9 V ~ 36 V，±4.5 V ~ 20 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
AD712
Rev. H | Page 11 of 20
)
SETTLING TIME
OPTIMIZING SETTLING TIME
Most bipolar high speed DACs have current outputs; therefore,
for most applications, an external op amp is required for a current-
to-voltage conversion. The settling time of the converter/op amp
combination depends on the settling time of the DAC and output
amplifier. A good approximation is
() (
2
AMP
t
DAC
t
Total
t
S
+
=
The settling time of an op amp DAC buffer varies with the noise
gain of the circuit, the DAC output capacitance, and the amount
of external compensation capacitance across the DAC output
scaling resistor.
Settling time for a bipolar DAC is typically 100 ns to 500 ns.
Previously, conventional op amps have required much longer
settling times than have typical state-of-the-art DACs; therefore,
the amplifier settling time has been the major limitation to a high
speed, voltage output, digital-to-analog function. The introduction
of the AD71x family of op amps with their 1 μs (to ±0.01% of
final value) settling time permits the full high speed capabilities
of most modern DACs to be realized.
In addition to a significant improvement in settling time, the
low offset voltage, low offset voltage drift, and high open-loop
gain of the AD71x family assure 12-bit accuracy over the full
operating temperature range.
The excellent high speed performance of the AD712 is shown in
were taken using a low input capacitance amplifier connected
directly to the summing junction of the AD712, and both figures
show a worst-case situation: full-scale input transition. The 4 kΩ
[10 kΩ||8 kΩ = 4.4 kΩ] output impedance of the DAC, together
with a 10 kΩ feedback resistor, produce an op amp noise gain of
3.25. The current output from the DAC produces a 10 V step at
the op amp output (0 to 10 V shown in Figure 29, and 10 V to
0 V shown in Figure 30).
Therefore, with an ideal op amp, settling to ±1/2 LSB (±0.01%)
requires that 375 μV or less appears at the summing junction.
This means that the error between the input and output (that
voltage which appears at the AD712 summing junction) must
be less than 375 μV. As shown in Figure 29, the total settling
time for the AD712/AD565A combination is 1.2 microseconds.
0V
–10V
OUTPUT
5V
1mV
SUMMING
JUNCTION
100
10
0%
90
500ns
0
08
23
-03
0
Figure 29. Settling Characteristics for AD712 with AD565A,
Full-Scale Negative Transition
0V
–10V
OUTPUT
5V
1mV
SUMMING
JUNCTION
100
10
0%
90
500ns
00
82
3-
03
1
Figure 30. Settling Characteristics for AD712 with AD565A,
Full-Scale Positive Transition
+15V
0.1F
10pF
OUTPUT
–10V TO +10V
AD565A
–15V
IREF
BIPOLAR
OFFSET ADJUST
IO
0.1F
R1
100
R2
100
GAIN
ADJUST
REF
IN
REF
GND
–VEE
0.1F
POWER
GND
MSB
LSB
8k
5k
5k
10V
19.95k
0.5mA
DAC
OUT
10V
SPAN
20V
SPAN
VCC
REF
OUT
BIPOLAR
OFF
9.95k
+
–
8
4
1/2
AD712
DAC
IOUT = 4 ×
IREF × CODE
20k
+
–
0
08
23
-02
9
Figure 31. ±10 V Voltage Output Bipolar DAC
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