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參數(shù)資料
| 型號： | AD712KRZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 0K |
| 描述： | IC OPAMP BIFET DUAL PREC 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 放大器類型： | J-FET |
| 電路數(shù)： | 2 |
| 轉(zhuǎn)換速率： | 20 V/µs |
| -3db帶寬： | 4MHz |
| 電流 - 輸入偏壓： | 20pA |
| 電壓 - 輸入偏移： | 200µV |
| 電流 - 電源： | 5mA |
| 電流 - 輸出 / 通道： | 25mA |
| 電壓 - 電源，單路/雙路(±)： | 9 V ~ 36 V，±4.5 V ~ 20 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
AD712
Rev. H | Page 12 of 20
OP AMP SETTLING TIME—A MATHEMATICAL
MODEL
The design of the AD712 gives careful attention to optimizing
individual circuit components; in addition, a careful trade-off
was made: the gain bandwidth product (4 MHz) and slew rate
(20 V/μs) were chosen to be high enough to provide very fast
settling time but not too high to cause a significant reduction
in phase margin (and therefore, stability). Thus designed, the
AD712 settles to ±0.01%, with a 10 V output step, in under 1 μs,
while retaining the ability to drive a 250 pF load capacitance
when operating as a unity-gain follower.
If an op amp is modeled as an ideal integrator with a unity-gain
crossover frequency of ωO/2π, then Equation 1 accurately
describes the small signal behavior of the circuit of Figure 32,
consisting of an op amp connected as an I-to-V converter at the
output of a bipolar or CMOS DAC. This equation would com-
pletely describe the output of the system if not for the finite slew
rate and other nonlinear effects of the op amp.
1
)
(
2
+
+
ω
+
ω
=
s
RC
G
s
C
R
I
V
f
O
N
O
X
IN
O
(1)
Where
π
ω
2
O = unity-gain frequency of the op amp.
GN = noise gain of circuit
+
O
R
1
.
This equation can then be solved for Cf
(
)
2
1
2
O
N
O
X
O
N
X
R
G
RC
R
G
C
ω
+
ω
+
ω
=
(2)
In these equations, Capacitance CX is the total capacitance
appearing at the inverting terminal of the op amp. When
modeling a DAC buffer application, the Norton equivalent
circuit shown in Figure 32 can be used directly; Capacitance CX
is the total capacitance of the output of the DAC plus the input
capacitance of the op amp (because the two are in parallel).
VOUT
RL
CL
CF
R
IO
RO
CX
1/2
AD712
+
–
0
082
3-
0
32
Figure 32. Simplified Model of the AD712 Used as a Current-Out DAC Buffer
When RO and IO are replaced with their Thevenin VIN and RIN
equivalents, the general-purpose inverting amplifier shown in
Figure 33 is created. Note that when using this general model,
Capacitance CX is either the input capacitance of the op amp, if
a simple inverting op amp is being simulated, or the combined
capacitance of the DAC output and the op amp input if the
DAC buffer is being modeled.
VOUT
RL
CL
CF
R
VIN
RIN
CX
1/2
AD712
+
–
00
82
3-
03
3
Figure 33. Simplified Model of the AD712 Used as an Inverter
In either case, Capacitance CX causes the system to go from a
one-pole to a two-pole response; this additional pole increases
settling time by introducing peaking or ringing in the op amp
output. Because the value of CX can be estimated with reasonable
accuracy, Equation 2 can be used to choose a small capacitor
(CF) to cancel the input pole and optimize amplifier response.
Figure 34 is a graphical solution of Equation 2 for the AD712
with R = 4 kΩ.
CF
C
X
40
30
0
10
0
20
10
50
60
GN = 4.0
GN = 3.0
20
30
40
50
60
GN = 2.0
GN = 1.5
GN = 1.0
00
82
3-
03
4
Figure 34. Value of Capacitor CF vs. Value of CX
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