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| 型號： | AD7147PACPZ-1RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/73頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CAP-TO-DGTL CONV PROG 24LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 系列： | CapTouch™ |
| 類型： | 電容數(shù)字轉(zhuǎn)換器 |
| 分辨率（位）： | 16 b |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | I²C，串行 |
| 電壓電源： | 單電源 |
| 電源電壓： | 2.6 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 帶卷 (TR) |
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Data Sheet
AD7147
Rev. D | Page 15 of 72
CAPACITIANCE-TO-DIGITAL CONVERTER
The capacitance-to-digital converter on the AD7147 has a Σ-Δ
architecture with 16-bit resolution. There are 13 possible inputs to
the CDC that are connected to the input of the converter through a
switch matrix. The sampling frequency of the CDC is 250 kHz.
OVERSAMPLING THE CDC OUTPUT
The decimation rate, or oversampling ratio, is determined by
Bits[9:8] of the power control (PWR_CONTROL) register
(Address 0x000), as listed in Table 9.
Table 9. CDC Decimation Rate
Decimation Bits
Decimation Rate
CDC Output Rate
Per Stage (ms)
00
256
3.072
01
128
1.536
10
64
0.768
11
64
0.768
The decimation process on the AD7147 is an averaging process,
where a number of samples are taken and the averaged result is
output. Due to the architecture of the digital filter employed, the
number of samples taken (per stage) is equal to 3× the decimation
rate. So 3 × 256 or 3 × 128 samples are averaged to obtain each
stage result.
The decimation process reduces the amount of noise present in
the final CDC result. However, the higher the decimation rate,
the lower the output rate per stage; therefore, there is a trade-off
possible between the amount of noise in the signal and the
speed of sampling.
CAPACITANCE SENSOR OFFSET CONTROL
There are two programmable DACs on board the AD7147 to null
the effect of any stray capacitances on the CDC measurement.
These offsets are due to stray capacitance to ground.
A simplified block diagram in Figure 24 shows how to apply the
STAGEx_AFE_OFFSET registers to null the offsets. The 6-bit
POS_AFE_OFFSET and NEG_AFE_OFFSET bits program the
offset DAC to provide 0.32 pF resolution offset adjustment over
a range of 20 pF.
The best practice is to ensure that the CDC output for any stage
is approximately equal to midscale (~32,700) when all sensors
are inactive. To correctly offset the stray capacitance to ground for
each stage, use the following procedure:
1.
Read back the CDC value from the CDC_RESULT_Sx register.
2.
If this value is not close to midscale, increase the value of
POS_AFE_OFFSET or NEG_AFE_OFFSET (depending
on if the CINx input is connected to the positive or negative
input of the converter) by 1. The CINx connections are
determined by the STAGEx_CONNECTION registers.
3.
If the CDC value in CDC_RESULT_Sx is now closer
to midscale, repeat Step 2. If the CDC value is further
from midscale, decrease the POS_AFE_OFFSET or
NEG_AFE_OFFSET value by 1.
The goal is to ensure that the CDC_RESULT_Sx is as close
to midscale as possible. This process is only required once
during the initial capacitance sensor characterization.
POS_AFE_OFFSET
16-BIT
CDC
NEG_AFE_OFFSET
+DAC
(20pF RANGE)
POS_AFE_OFFSET_SWAP BIT
NEG_AFE_OFFSET_SWAP BIT
6
16
CINx
+
_
CINx_CONNECTION_SETUP
–DAC
(20pF RANGE)
06
66
3-
02
1
Figure 24. Analog Front-End Offset Control
CONVERSION SEQUENCER
The AD7147 has an on-chip sequencer to implement conversion
control for the input channels. Up to 12 conversion stages can be
performed in one sequence. Each of the 12 conversions stages can
measure the input from a different sensor. By using the Bank 2
registers, each stage can be uniquely configured to support multiple
capacitance sensor interface requirements. For example, a slider
sensor can be assigned to STAGE1 through STAGE8, with a
button sensor assigned to STAGE0. For each conversion stage,
the input mux that connects the CINx inputs to the converter
can have a unique setting.
The AD7147 on-chip sequence controller provides conversion
control, beginning with STAGE0. Figure 25 shows a block diagram
of the CDC conversion stages and CINx inputs. A conversion
sequence is defined as a sequence of CDC conversions starting
at STAGE0 and ending at the stage determined by the value
programmed in the SEQUENCE_STAGE_NUM bits. Depending
on the number and type of capacitance sensors that are used, not all
conversion stages are required. Use the SEQUENCE_STAGE_NUM
bits to set the number of conversions in one sequence. This number
depends on the sensor interface requirements. For example, the
register should be set to 5 if the CINx inputs are mapped to only six
conversion stages. In addition, the STAGE_CAL_EN register
should be set according to the number of stages that are used.
The number of required conversion stages depends solely on
the number of sensors attached to the AD7147. Figure 26 shows
how many conversion stages are required for each sensor and
how many inputs to the AD7147 each sensor requires.
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