參數(shù)資料
型號: AD7147PACPZ-RL
廠商: Analog Devices Inc
文件頁數(shù): 38/73頁
文件大小: 0K
描述: IC CAP-TO-DGTL CONV PROG 24LFCSP
標(biāo)準(zhǔn)包裝: 5,000
系列: CapTouch™
類型: 電容數(shù)字轉(zhuǎn)換器
分辨率(位): 16 b
采樣率(每秒): 250k
數(shù)據(jù)接口: 串行,SPI?
電壓電源: 單電源
電源電壓: 2.6 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 24-LFCSP-VQ(4x4)
包裝: 帶卷 (TR)
AD7147
Data Sheet
Rev. D | Page 42 of 72
REGISTER MAP
The AD7147 address space is divided into three register banks,
referred to as Bank 1, Bank 2, and Bank 3. Figure 62 illustrates
the division of these banks.
Bank 3 registers contain the results of each conversion stage.
These registers automatically update at the end of each conversion
sequence. Although these registers are primarily used by the
AD7147 internal data processing, they are accessible by the host
processor for additional external data processing, if desired.
Bank 1 registers contain control registers, CDC conversion
control registers, interrupt enable registers, interrupt status
registers, CDC 16-bit conversion data registers, device ID
registers, and proximity status registers.
Default values are undefined for Bank 2 registers and Bank 3
registers until after power-up and configuration of the Bank 2
registers.
Bank 2 registers contain the configuration registers used to
configure the individual CINx inputs for each conversion stage.
Initialize the Bank 2 configuration registers immediately after
power-up to obtain valid CDC conversion result data.
06
66
3-
0
59
BANK 1 REGISTERS
ADDR 0x000
ADDR 0x018
ADDR 0x001
ADDR 0x005
ADDR 0x008
ADDR 0x00B
ADDR 0x017
ADDR 0x7F0
BANK 2 REGISTERS
ADDR 0x080
ADDR 0x0B8
ADDR 0x0C0
ADDR 0x0C8
ADDR 0x0D0
ADDR 0x0D8
ADDR 0x088
ADDR 0x090
ADDR 0x098
ADDR 0x0A0
ADDR 0x0A8
ADDR 0x0B0
BANK 3 REGISTERS
ADDR 0x0E0
ADDR 0x088
ADDR 0x090
ADDR 0x098
ADDR 0x0A0
ADDR 0x0A8
ADDR 0x042
ADDR 0x043
INVALID DO NOT ACCESS
PROXIMITY STATUS REGISTER
(1 REGISTER)
INVALID DO NOT ACCESS
DEVICE ID REGISTER
(1 REGISTER)
CDC 16-BIT CONVERSION DATA
(12 REGISTERS)
INTERRUPT STATUS
(3 REGISTERS)
INTERRUPT ENABLE
(3 REGISTERS)
CALIBRATION AND SETUP
(4 REGISTERS)
SETUP CONTROL
(1 REGISTER)
96
R
EG
IST
ER
S
43
2RE
G
IS
T
E
R
S
STAGE7 CONFIGURATION
(8 REGISTERS)
STAGE6 CONFIGURATION
(8 REGISTERS)
STAGE8 CONFIGURATION
(8 REGISTERS)
STAGE9 CONFIGURATION
(8 REGISTERS)
STAGE10 CONFIGURATION
(8 REGISTERS)
STAGE11 CONFIGURATION
(8 REGISTERS)
STAGE5 CONFIGURATION
(8 REGISTERS)
STAGE4 CONFIGURATION
(8 REGISTERS)
STAGE3 CONFIGURATION
(8 REGISTERS)
STAGE2 CONFIGURATION
(8 REGISTERS)
STAGE1 CONFIGURATION
(8 REGISTERS)
STAGE0 CONFIGURATION
(8 REGISTERS)
STAGE7 RESULTS
(36 REGISTERS)
STAGE6 RESULTS
(36 REGISTERS)
STAGE8 RESULTS
(36 REGISTERS)
STAGE9 RESULTS
(36 REGISTERS)
STAGE10 RESULTS
(36 REGISTERS)
STAGE11 RESULTS
(36 REGISTERS)
STAGE5 RESULTS
(36 REGISTERS)
STAGE4 RESULTS
(36 REGISTERS)
STAGE3 RESULTS
(36 REGISTERS)
STAGE2 RESULTS
(36 REGISTERS)
STAGE1 RESULTS
(36 REGISTERS)
STAGE0 RESULTS
(36 REGISTERS)
26
RE
G
IS
T
ERS
ADDR 0x0B8
ADDR 0x0C0
ADDR 0x0C8
ADDR 0x0D0
ADDR 0x28F
ADDR 0x0B0
Figure 62. Layout of Bank 1, Bank 2, and Bank 3 Registers
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