參數(shù)資料
型號(hào): AD7147WPACPZ-500R7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 30/73頁(yè)
文件大?。?/td> 0K
描述: IC CAP-TO-DGTL CONV PROG 24LFCSP
標(biāo)準(zhǔn)包裝: 500
系列: CapTouch™
類型: 電容數(shù)字轉(zhuǎn)換器
分辨率(位): 16 b
采樣率(每秒): 250k
數(shù)據(jù)接口: 串行,SPI?
電壓電源: 單電源
電源電壓: 2.6 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 24-LFCSP-VQ(4x4)
包裝: 帶卷 (TR)
Data Sheet
AD7147
Rev. D | Page 35 of 72
SDI
CW
15
CW
14
CW
13
CW
8
CW
1
CW
0
D15 D14
SCLK
CW
12
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN).
4. CS IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION:
CW [15:11] = 11100 (ENABLE WORD)
CW [10] = 0 (R/W)
CW [9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB-JUSTIFIED REGISTER ADDRESS)
D1
D0
D1
D0
D15
DATA FOR STARTING
REGISTER ADDRESS
DATA FOR NEXT
REGISTER ADDRESS
D15
D14
1
32
234
15
16
17
18
31
34
33
48
47
49
CS
CW
11
CW
10
CW
9
CW
7
CW
2
CW
6
CW
5
CW
4
CW
3
11
12
13
14
56
7
8
910
ENABLE WORD
R/W
STARTING REGISTER ADDRESS
16-BIT COMMAND WORD
0
6663
-04
7
Figure 50. Sequential Register Write SPI Timing
CW
11
CW
10
CW
13
CW
12
SDI
CW
15
CW
14
CW
9
CW
7
CW
6
CW
5
CW
4
CW
3
CW
2
CW
1
CW
0
XX
X
CW
8
t1
t4
16-BIT READBACK DATA
5
32
6
7
8
9
10
11
12
13
14
15
16
30
31
t8
t5
SCLK
12
3
4
XX
X
17
18
19
CS
XXX
SDO
XXX
D2
D1
D0
XXX
D15
D14
D13
t6
t7
XXX
ENABLE WORD
R/W
REGISTER ADDRESS
t2
t3
16-BIT COMMAND WORD
NOTES
1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS.
3. THE REGISTER DATA IS READ BACK ON THE SDO PIN.
4. X DENOTES DON’T CARE.
5. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.
6. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.
7. 16-BIT COMMAND WORD SETTINGS FOR SINGLE READBACK OPERATION:
CW [15:11] = 11100 (ENABLE WORD)
CW [10] = 1 (R/W)
CW [9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB-JUSTIFIED REGISTER ADDRESS)
066
63-
048
Figure 51. Single Register Readback SPI Timing
Reading Data
A read transaction begins when the master writes the command
word to the AD7147 with the read/write bit set to 1. The master
then supplies 16 clock pulses per data-word to be read, and the
AD7147 clocks out data from the addressed register on the SDO
line. The first data-word is clocked out on the first falling edge
of SCLK following the command word, as shown in Figure 51.
The AD7147 continues to clock out data on the SDO line if the
master continues to supply the clock signal on SCLK. The read
transaction finishes when the master takes CS high. If the AD7147
address pointer reaches its maximum value, the AD7147 repeatedly
clocks out data from the addressed register. The address pointer
does not wrap around.
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