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| 型號： | AD7225KP-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT QUAD W/AMP 28-PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 設(shè)置時間： | 4µs |
| 位數(shù)： | 8 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 500mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 200k |
AD7225
Rev. C | Page 17 of 24
APPLICATIONS INFORMATION
h1
1
T
Xn
h2
2
T
Xn – 1
h3
3
T
Xn – 2
h4
4
Xn – 3
FILTER
INPUT
+
y(n)
FILTER
OUTPUT
AD7225
QUAD DAC
+
AD585
SHA
AD7225
QUAD DAC
AD7820
ADC
INPUT
SAMPLES
AM29520
TLC
DELAYED
INPUT
SAMPLES
AD584
REF
10V
VREF
AM7224
DAC
VOUT
VREF
VREFA
VOUTA
h1
VREFA
VOUTA
h2
VREFA
VOUTA
h3
VREFA
VOUTA
h4
TAP WEIGHT
GAIN SET
VOUTA
VOUTB
VOUTC
VOUTD
ACCUMULATOR
OUTPUT
FILTER
OUTPUT
00986-
020
Figure 20. Programmable Transversal Filter
PROGRAMMABLE TRANSVERSAL FILTER
A discrete time filter can be described by either multiplication
in the frequency domain or by convolution in the time domain:
( )
( ) ( )
∑
=
+
=
ω
=
ω
N
k
n
k
n
X
h
y
or
X
H
Y
1
The convolution sum can be implemented using the special struc-
ture known as the transversal filter (see Figure 21). It consists
of an N-stage delay line with N taps weighted by N coefficients,
the resulting products being accumulated to form the output.
The tap weights or coefficients hk are the nonzero elements of
the impulse response and therefore determine the filter transfer
function. A particular filter frequency response is realized by
setting the coefficients to the appropriate values. This property
leads to the implementation of transversal filters whose fre-
quency response is programmable.
h1
1
T
Xn
h2
2
T
Xn – 1
h3
3
Xn – 2
hN
N
Xn – N + 1
hN – 1
N –1
T
Xn – N
FILTER
INPUT
+
Xn – k + 1
hk
yn =
N
k = 1
FILTER
OUTPUT
00986-
021
Figure 21. Transversal Filter
A four-tap programmable transversal filter can be implemented
using the AD7225 (see Figure 20). The input signal is first sampled
and converted to allow the tapped delay line function to be
provided by the AM29520. The multiplication of delayed input
samples by fixed, programmable up weights is accomplished by
the AD7225, the four coefficients or reference inputs being set
by the digital codes stored in the AD7226. The resultant products
are accumulated to yield the convolution sum output sample,
which is held by the AD585.
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
G
AI
N
(
d
B)
NORMALIZED FREQUENCY (f/fS)
h1 = 0.117
h2 = 0.417
h3 = 0.417
h4 = 0.417
00986-
022
Figure 22. Predicted (Theoretical) Response
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
G
AI
N
(
d
B)
FREQUENCY (f/fS)
h1 (DAC A) = 00011110
h2 (DAC B) = 01101011
h3 (DAC C) = 01101011
h4 (DAC D) = 00011110
00986-
023
Figure 23. Actual Response
Low-pass, band-pass, and high-pass filters can be synthesized
using this arrangement. The particular up weights needed for
any desired transfer function can be obtained using the standard
Remez exchange algorithm. Figure 22 shows the theoretical
low-pass frequency response produced by a four-tap transversal
filter with the coefficients indicated. Although the theoretical
prediction does not take into account the quantization of the
input samples and the truncation of the coefficients, neverthe-
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| AD7225KPZ | 功能描述:IC DAC 8BIT QUAD W/AMP 28-PLCC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD7225KR | 功能描述:IC DAC 8BIT QUAD W/AMP 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,400 系列:- 設(shè)置時間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應(yīng)商設(shè)備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率（每秒）:* |
| AD7225KR-REEL | 功能描述:IC DAC 8BIT QUAD W/AMP 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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