參數(shù)資料
型號: AD7225LR
廠商: Analog Devices Inc
文件頁數(shù): 3/24頁
文件大?。?/td> 0K
描述: IC DAC 8BIT QUAD W/AMP 24-SOIC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 31
設(shè)置時間: 4µs
位數(shù): 8
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 雙 ±
功率耗散(最大): 500mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SOIC W
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): 200k
AD7225
Rev. C | Page 11 of 24
GROUND MANAGEMENT AND LAYOUT
Because the AD7225 contains four reference inputs that can be
driven from ac sources (see the AC Reference Signal section),
careful layout and grounding is important to minimize analog
crosstalk between the four channels. The dynamic performance
of the four DACs depends on the optimum choice of board
layout. Figure 14 shows the relationship between input fre-
quency and channel-to-channel isolation. Figure 15 shows a
printed circuit board layout that minimizes crosstalk and
feedthrough. The four input signals are screened by AGND.
VREF was limited to between 2 V and 3.24 V to avoid slew rate
limiting effects from the output amplifier during measurements.
–80
–70
–60
–50
–40
–30
20k
50k
100k
200k
500k
1M
IS
OLA
TION
(
dB
)
INPUT FREQUENCY (Hz)
VDD = +15V
VSS = –5V
TA = 25°C
VREF = 1.24V p-p
00986-
014
Figure 14. Channel-to-Channel Isolation
VOUTC
VOUTB
VOUTD
VOUTA
VDD
VSS
VREFC
VREFB
VREFD
VREFA
MSB
LSB
PIN 1
SYSTEM
GND
DGND
AGND
00986-
015
Figure 15. Suggested PCB Layout for AD7225, Component Side (Top View)
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