參數(shù)資料
型號(hào): AD7225LR
廠商: Analog Devices Inc
文件頁(yè)數(shù): 6/24頁(yè)
文件大?。?/td> 0K
描述: IC DAC 8BIT QUAD W/AMP 24-SOIC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 31
設(shè)置時(shí)間: 4µs
位數(shù): 8
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 雙 ±
功率耗散(最大): 500mW
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SOIC W
包裝: 管件
輸出數(shù)目和類(lèi)型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): 200k
AD7225
Rev. C | Page 14 of 24
BIPOLAR OUTPUT OPERATION
Each of the DACs of the AD7225 can be individually confi-
gured to provide bipolar output operation. This is possible
using one external amplifier and two resistors per channel.
Figure 17 shows a circuit used to implement offset binary
coding (bipolar operation) with DAC A (DAC Channel A)
of the AD7225. In this case,
(
)
(
)
REF
A
OUT
V
R
R2
V
D
R1
R2
V
×
×
+
=
1
With R1 = R2
(
) ( )
REF
A
OUT
V
D
V
×
=
1
2
where DA is a fractional representation of the digital word in
Latch A (0 ≤ DA ≤ 255/256).
Mismatch between R1 and R2 causes gain and offset errors and,
therefore, these resistors must match and track over tempera-
ture. The AD7225 can be operated in single supply or from
positive/negative supplies. Table 8 shows the digital code vs.
output voltage relationship for the circuit of Figure 17 with
R1 = R2.
+15V
–15V
VDD
VSS
AGND
DGND
VOUTA
DAC A
AD7225*
VREFA
R2
VOUT
R1
VREF
R1, R2 = 10k
± 0.1%.
*DIGITAL INPUTS OMITTED
FOR CLARITY.
00986-
017
Figure 17. Bipolar Output Circuit
Table 8. Bipolar (Offset Binary) Code Table
DAC Latch Contents
Analog Output
MSB
LSB
1111
( )
128
127
REF
V
+
1000
0001
( )
128
1
REF
V
+
1000
0000
0 V
0111
1111
( )
128
1
REF
V
0000
0001
( )
128
127
REF
V
0000
( )
REF
V
=
1
128
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