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參數(shù)資料
| 型號(hào)： | AD7228LPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DAC 8BIT OCTAL W/AMP 28-PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 5µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 310mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 管件 |
| 輸出數(shù)目和類(lèi)型： | 8 電壓，單極；8 電壓，雙極 |
| 采樣率（每秒）： | 200k |
AD7228A
REV. A
–6–
Table II. Unipolar Code Table
DAC Latch Contents
MSB
LSB
Analog Output
1 1 1 1
+V
REF
255
256
1 0 0 0
0 0 0 1
+V
REF
129
256
1 0 0 0
0 0 0 0
+V
REF
128
256
=+
V
REF
2
0 1 1 1
1 1 1 1
+V
REF
127
256
0 0 0 0
0 0 0 1
+V
REF
1
256
0 0 0 0
0 V
Note: 1 LSB = (VREF)(2
–8) = V
REF
1
256
BIPOLAR OUTPUT OPERATION
Each of the DACs on the AD7228A can be individually config-
ured for bipolar output operation. This is possible using one ex-
ternal amplifier and two resistors per channel. Figure 8 shows a
circuit used to implement offset binary coding (bipolar opera-
tion) with DAC1 of the AD7228A. In this case
V
OUT =
1
+ R2
R1
D
1 V REF
() – R2
R1
V
REF
()
With R1 = R2
VOUT = (2D1 – 1) (VREF)
where D1 is a fractional representation of the digital word in
latch 1 of the AD7228A. (0
≤ D
1
≤ 255/256)
Figure 8. Bipolar Output Circuit
Table III. Bipolar Code Table
DAC Latch Contents
MSB
LSB
Analog Output
1 1 1 1
+V
REF
127
128
1 0 0 0
0 0 0 1
+V
REF
1
128
1 0 0 0
0 0 0 0
0 V
0 1 1 1
1 1 1 1
–V
REF
1
128
0 0 0 0
0 0 0 1
–V
REF
127
128
0 0 0 0
–V
REF
128
= –V
REF
Mismatch between R1 and R2 causes gain and offset errors, and
therefore, these resistors must match and track over temperature.
Once again, the AD7228A can be operated from single supply
or from dual supplies. Table III shows the digital code versus
output voltage relationship for the circuit of Figure 8 with
R1 = R2.
AC REFERENCE SIGNAL
In some applications it may be desirable to have an ac signal ap-
plied as the reference input to the AD7228A. The AD7228A
has multiplying capability within the upper (+10 V) and lower
(+2 V) limits of reference voltage when operated with dual sup-
plies. Therefore, ac signals need to be ac coupled and biased up
before being applied to the reference input. Figure 9 shows a
sine-wave signal applied to the reference input of the AD7228A.
For input frequencies up to 50 kHz, the output distortion typi-
cally remains less than 0.1%. The typical 3 dB bandwidth for
small signal inputs is 800 kHz.
Figure 9. Applying a AC Signal to the AD7228A
TIMING DESKEW
A common problem in ATE applications is the slowing or
“rounding-off” of signal edges by the time they reach the
pin-driver circuitry. This problem can easily be overcome by
“squaring-up” the edge at the pin-driver. However, since each
edge will not have been “rounded-off” by the same extent, this
“squaring-up” could lead to incorrect timing relationship be-
tween signals. This effect is shown in Figure 10a.
Figure 10a. Time Skewing Due to Slowing of Edges
The circuit of Figure 10b shows how two DACs of the
AD7228A can help in overcoming this problem. The same two
signals are applied to this circuit as were applied in Figure 10b.
The output of each DAC is applied to one input of a high-speed
comparator, and the signals are applied to the other inputs.
Varying the output voltage of the DAC effectively varies the
trigger point at which the comparator flips. Thus the timing re-
lationship between the two signals can be programmably cor-
rected (or deskewed) by varying the code to the DAC of the
AD7228A. In a typical application, the code is loaded to the
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