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參數(shù)資料
| 型號： | AD7228LPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT OCTAL W/AMP 28-PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 5µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 310mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 8 電壓，單極；8 電壓，雙極 |
| 采樣率（每秒）： | 200k |
AD7228A
REV. A
–7–
DACs for correct timing relationships during the calibration
cycle of the instrument.
Figure 10b. AD7228A Timing Deskew Circuit
COARSE/FINE ADJUST
The DACs on the AD7228A can be paired together to form a
coarse/fine adjust function as indicated in Figure 11. The func-
tion is achieved using one external op amp and a few resistors
per pair of DACs.
DAC1 is the most significant or coarse DAC. Data is first
loaded to this DAC to coarsely set the output voltage. DAC2 is
then used to fine tune this output voltage. Varying the ratio of
R1 to R2 varies the relative effect of the coarse and fine DACs
on the output voltage. For the resistor values shown, DAC2 has
a resolution of 150
V in a 10 V output range. Since each DAC
on the AD7228A is guaranteed monotonic, the coarse adjust-
ment and fine adjustment are each monotonic. One application
for this is as a set-point controller (see “Circuit Applications of
the AD7226 Quad CMOS DAC” available from Analog Devices,
Publication Number E873–15–11/84).
Figure 11. Coarse/Fine Adjust Circuit
SELF-PROGRAMMABLE REFERENCE
The circuit of Figure 12 shows how one DAC of the AD7228,
in this case DAC1, may be used in a feedback configuration to
provide a programmable reference for itself and the other seven
converters. The relationship of VREF to VIN is expressed by
V
REF =
1
+ G
()
1
+ G D
1
()
V
IN
where G = R2/R1
Figure 13 shows typical plots of VREF versus digital code, D1, for
three different values of G. With VIN = 2.5 V and G = 3 the
voltage at the output varies between 2.5 V and 10 V giving an
effective 10-bit dynamic range to the other seven converters. For
correct operation of the circuit, VSS should be –5 V and R1
greater than 6.8 k
.
Figure 12. Self-Programmable Reference
Figure 13. Variation of VREF with Feedback Configuration
MICROPROCESSOR INTERFACING
Figure 14. AD7228A to 8085A/Z80 Interface
Figure 15. AD7228A to 6809/6502 Interface
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