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參數(shù)資料
| 型號： | AD7249BNZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/14頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT SRL W/REF 16DIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 系列： | DACPORT® |
| 設(shè)置時間： | 10µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 300mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 16-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 16-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | 125k |
–4–
AD7249
PIN FUNCTION DESCRIPTION (DIP & SOIC PIN NUMBERS)
Pin
Mnemonic
Description
11
REFOUT
Voltage Reference Output. The internal 5 V analog reference is provided at this pin. To operate the
part using its internal reference, REFOUT should be connected to REFIN.
12
REFIN
Voltage Reference Input. It is internally buffered before being applied to both DACs. The nominal
reference voltage for specified operation of the AD7249 is 5 V.
13ROFSB
Output Offset Resistor for the amplifier of DAC B. It is connected to VOUTB for the +5 V range, to
AGND for the +10 V range and to REFIN for the –5 V to +5 V range.
14VOUTB
Analog Output Voltage of DAC B. This is the buffer amplifier output voltage. Three different output
voltage ranges can be chosen: 0 V to +5 V, 0 V to +10 V and –5 V to +5 V.
15
AGND
Analog Ground. Ground reference for all analog circuitry.
16
CLR
Clear, Logic Input. Taking this input low clears both DACs. It sets VOUTA and VOUTB to 0 V in both
unipolar ranges and the twos complement bipolar range and to –REFIN in the offset binary bipolar
range.
17
BIN/COMP
Logic Input. This input selects the data format to be either binary or twos complement. In both uni-
polar ranges natural binary format is selected by connecting this input to a Logic “0”. In the bipolar
configuration offset binary format is selected with a Logic “0” while a Logic “1” selects twos complement.
18
DGND
Digital Ground. Ground reference for all digital circuitry.
19
SDIN
Serial Data In, Logic Input. The 16-bit serial data word is applied to this input.
10
LDAC
Load DAC, Logic Input. Updates both DAC outputs. The DAC outputs are updated on the falling
edge of this signal or alternatively if this line is permanently low, an automatic update mode is se-
lected whereby both DACs are updated on the 16th falling SCLK pulse.
11
SCLK
Serial Clock, Logic Input. Data is clocked into the input register on each falling SCLK edge.
12
SYNC
Data Synchronization Pulse, Logic Input. Taking this input low initializes the internal logic in readi-
ness for a new data word.
13
VDD
Positive Power Supply.
14
VOUTA
Analog Output Voltage of DAC A. This is the buffer amplifier output voltage. Three different output
voltage ranges can be chosen: 0 V to +5 V, 0 V to +10 V and –5 V to +5 V.
15
VSS
Negative Power Supply (used for the output amplifier only) may be connected to 0 V for single sup-
ply operation or –12 V to –15 V for dual supplies.
16
ROFSA
Output Offset Resistor for the amplifier of DAC A. It is connected to VOUTA for the +5 V range, to
AGND for the +10 V range and to REFIN for the –5 V to +5 V range.
PIN CONFIGURATIONS
(DIP and SOIC)
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
REFOUT
ROFSA
AD7249
REFIN
VSS
ROFSB
VOUTA
VOUTB
VDD
AGND
SYNC
CLR
SCLK
BIN/COMP
LDAC
DGND
SDIN
REV. D
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