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參數(shù)資料
| 型號(hào)： | AD7249BRZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 13/14頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT SRL W/REF 16SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | DACPORT® |
| 設(shè)置時(shí)間： | 10µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 300mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | 125k |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)當(dāng)前第13頁(yè)第14頁(yè)
–8–
AD7249
t2
t5
t4
t3
t10
t6
t7
t8
t9
DB15
DB14
DB13
DB12
DB11
DB0
DB15
DB14
DB13
DB12
DB10
DB0
DON'T
CARE
DON'T
CARE
DON'T
CARE
DAC
SELECT
=0
MSB
DON'T
CARE
DON'T
CARE
DON'T
CARE
DAC
SELECT
=1
MSB
LSB
DAC A
DAC B
t1
SCLK
SYNC
SDIN
LDAC
CLR
Figure 8. Timing Diagram
TRANSFER FUNCTION
The internal scaling resistors provided on the AD7249 allow
several output voltage ranges. The part can produce unipolar
output ranges of 0 V to +5 V or 0 V to +10 V and a bipolar
output range of
±5 V. Connections for the various ranges are
outlined below. Since each DAC has its own ROFS input the two
DACs can be set up for different output ranges.
Unipolar (0 V to +10 V) Configuration
The first of the configurations provides an output voltage range
of 0 V to +10 V. This is achieved by connecting the output
offset resistor ROFSA, ROFSB (Pin 3, 16) to AGND. Natural Bi-
nary data format is selected by connecting
BIN/COMP (Pin 7)
to DGND. In this configuration, the AD7249 can be operated
using either single or dual supplies. Note that the VDD supply is
AD7249*
VDD
2R
A1
A2
12-BIT
DAC A
12-BIT
DAC B
REFOUT
REFIN
ROFSA
VOUTA
0V TO 10V
ROFSB
VOUTB
0V TO 10V
BIN/COMP
DGND
AGND
0V OR VSS
VSS
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 9. Unipolar (0 V to +10 V) Configuration
restricted to +15 V
± 10% for this range in order to maintain
sufficient amplifier headroom. Dual supplies may be used to
improve settling time and give increased current sink capability
for the amplifier. Figure 9 shows the connection diagram for
unipolar operation of the AD7249. Table I shows the digital
code vs. analog output for this configuration.
Unipolar (0 V to +5 V) Configuration
The 0 V to +5 V output voltage range is achieved by tying
ROFSA to VOUTA or ROFSB to VOUTB. Once again, the AD7249
can be operated using either single or dual supplies. The table
for output voltage versus digital code is as in Table I, with
2REFIN replaced by REFIN. Note, for this range, 1 LSB =
REFIN
× (2–12) = (REFIN/4096).
Table I. Unipolar Code Table (0 V to +10 V Range)
Input Data Word
MSB
LSB
Analog Output, VOUT
XXXY 1111 1111 1111
+2REFIN
× (4095/4096)
XXXY 1000 0000 0001
+2REFIN
× (2049/4096)
XXXY 1000 0000 0000
+2REFIN
× (2048/4096) = +REFIN
XXXY 0111 1111 1111
+2REFIN
× (2047/4096)
XXXY 0000 0000 0001
+2REFIN
× (1/4096)
XXXY 0000 0000 0000
0 V
X = Don’t Care.
Y = DAC Select Bit, 0 = DAC A, 1= DAC B.
Note: 1 LSB = 2REFIN/4096.
REV. D
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