參數(shù)資料
型號(hào): AD725AR-REEL7
廠商: ANALOG DEVICES INC
元件分類: 顏色信號(hào)轉(zhuǎn)換
英文描述: Low Cost RGB to NTSC/PAL Encoder with Luma Trap Port
中文描述: COLOR SIGNAL ENCODER, PDSO16
封裝: SOIC-16
文件頁(yè)數(shù): 4/20頁(yè)
文件大?。?/td> 347K
代理商: AD725AR-REEL7
REV. 0
–4–
AD725
PIN DE SCRIPT IONS
Pin
Mnemonic
Description
E quivalent Circuit
1
ST ND
Encoding Standard Pin. A Logic HIGH input selects NT SC encoding.
A Logic LOW input selects PAL encoding.
T T L Logic Levels.
Analog Ground Connection.
4FSC Clock Input.
For NT SC: 14.318 180 MHz.
For PAL: 17.734 475 MHz.
T T L Logic Levels.
Analog Positive Supply (+5 V
±
5%).
Chip Enable. A Logic HIGH input enables the encode function.
A Logic LOW input powers down chip when not in use.
T T L Logic Levels.
Red Component Video Input.
0 mV to 714 mV AC-Coupled.
Green Component Video Input.
0 mV to 714 mV AC-Coupled.
Blue Component Video Input.
0 mV to 714 mV AC-Coupled.
Chrominance Output.*
Approximately 1.8 V peak-to-peak for both NT SC and PAL.
Composite Video Output.*
Approximately 2.5 V peak-to-peak for both NT SC and PAL.
Luminance plus CSYNC Output.*
Approximately 2 V peak-to-peak for both NT SC and PAL.
Luminance T rap Filter T ap. Attach L-C resonant network to reduce cross-color artifacts.
Digital Ground Connection.
Digital Positive Supply (+5 V
±
5%).
Vertical Sync Signal (if using external CSYNC set at > +2 V). T T L Logic Levels.
Horizontal Sync Signal (or CSYNC signal). T T L Logic Levels.
Circuit A
2
3
AGND
4FSC
Circuit A
4
5
APOS
CE
Circuit A
6
RIN
Circuit B
7
GIN
Circuit B
8
BIN
Circuit B
9
CRMA
Circuit C
10
COMP
Circuit C
11
LUMA
Circuit C
12
13
14
15
16
YT RAP
DGND
DPOS
VSYNC
HSYNC
Circuit D
Circuit A
Circuit A
*T he Luminance, Chrominance and Composite Outputs are at twice normal levels for driving 75
reverse-terminated lines.
7
V
CLAMP
6
8
DPOS
DGND
3
1
5
15
16
DPOS
DGND
10
9
11
APOS
AGND
DGND
DPOS
APOS
AGND
DGND
DPOS
12
1k
V
Circuit A
Circuit B
Circuit C
Circuit D
Figure 1. Equivalent Circuits
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