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參數(shù)資料
| 型號(hào)： | AD7266ACP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Differential Input, Dual 2 MSPS, 12-Bit, 3-Channel SAR ADC |
| 中文描述： | DUAL 3-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, QCC32 |
| 封裝： | MO-220-VHHD-2, LFCSP-32 |
| 文件頁(yè)數(shù)： | 10/17頁(yè) |
| 文件大?。?/td> | 752K |
| 代理商： | AD7266ACP |
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AD7266
Preliminary Technical Data
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7266 is a fast, micropower, dual 12-bit, single supply,
A/D converter that operates from a 2.7 V to 5.25 V supply.
When operated from a 5 V supply, the AD7266 is capable of
throughput rates of 2 MSPS when provided with a TBD MHz
clock, and a throughput rate of 1.5 MSPS at 3 V.
0
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
A
B
B
SW2
C
S
C
S
V
IN+
V
IN–
V
REF
The AD7266 contains two on-chip differential track-and-hold
amplifiers, two successive approximation A/D converters, and a
serial interface with two separate data output pins, and is
housed in a 32-lead LFCSP package, which offers the user
considerable space-saving advantages over alternative solutions.
The serial clock input accesses data from the part but also
provides the clock source for each successive approximation
ADC. The analog input range for the part can be selected to be a
0 V to V
REF
input or a 2 × V
REF
input with the analog inputs
configured as either single ended or differential. The AD7266
has an on-chip 2.5 V reference that can be overdriven if an
external reference is preferred.
Figure 3. ADC Acquisition Phase
When the ADC starts a conversion (Figure 4), SW3 opens and
SW1 and SW2 move to position B, causing the comparator to
become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistribu-
tion DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the ADC output code. The output impedances of the
sources driving the V
IN+
and V
IN–
pins must be matched;
otherwise, the two inputs will have different settling times,
resulting in errors.
The AD7266 also features power-down options to allow power
saving between conversions. The power-down feature is
implemented across the standard serial interface, as described in
the Modes of Operation section.
CONVERTER OPERATION
The AD7266 has two successive approximation analog-to-
digital converters, each based around two capacitive DACs.
Figure 3 and Figure 4 show simplified schematics of one of
these ADCs in acquisition and conversion phase, respectively.
The ADC is comprised of control logic, a SAR, and two
capacitive DACs. In Figure 3 (the acquisition phase), SW3, is
closed, SW1 and SW2 are in position A, the comparator is held
in a balanced condition, and the sampling capacitor arrays
acquire the differential signal on the input.
0
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
A
B
B
SW2
C
S
C
S
V
IN+
V
IN–
V
REF
Figure 4. ADC Conversion Phase
Rev. PrG | Page 10 of 17
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7266ASU | 制造商:Analog Devices 功能描述:ADC DUAL SAR 2MSPS 12-BIT SERL 32TQFP - Bulk |
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| AD7266BCPZ | 功能描述:IC ADC 12BIT 3CH 2MSPS 32-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個(gè)單端，單極 產(chǎn)品目錄頁(yè)面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7266BCPZ-REEL | 功能描述:IC ADC 12BIT 3CHAN 2MSPS 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端，單極 |
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