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參數(shù)資料
| 型號(hào)： | AD7266ACP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Differential Input, Dual 2 MSPS, 12-Bit, 3-Channel SAR ADC |
| 中文描述： | DUAL 3-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, QCC32 |
| 封裝： | MO-220-VHHD-2, LFCSP-32 |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 752K |
| 代理商： | AD7266ACP |
Preliminary Technical Data
AD7266
MODES OF OPERATION
The mode of operation of the AD7266 is selected by controlling
the (logic) state of the CS signal during a conversion. There are
three possible modes of operation: normal mode, partial power-
down mode, and full power-down mode. The point at which CS
is pulled high after the conversion has been initiated determines
which power-down mode, if any, the device enters. Similarly, if
already in a power-down mode, CS can control whether the
device returns to normal operation or remains in power-down.
These modes of operation are designed to provide flexible
power management options. These options can be chosen to
optimize the power dissipation/throughput rate ratio for
differing application requirements.
accessed on the same DOUT line, as shown in Figure TBD (see
the Serial Interface section). The identification bit provided
prior to each conversion result identifies which on-board ADC
the following result is from. Once 32 SCLK cycles have elapsed,
the DOUT line returns to three-state on the 32
nd
SCLK falling
edge. If CS is brought high prior to this, the DOUT line returns
to three-state at that point. Thus, CS may idle low after 32 SCLK
cycles until it is brought high again sometime prior to the next
conversion (effectively idling CS low), if so desired, since the
bus still returns to three-state upon completion of the dual
result read.
Once a data transfer is complete and D
OUT
A and D
OUT
B have
returned to three-state, another conversion can be initiated after
the quiet time, t
QUIET
, has elapsed by bringing CS low again.
NORMAL MODE
This mode is intended for fastest throughput rate performance
since the user does not have to worry about any power-up times
with the AD7266 remaining fully powered all the time. Figure 8
shows the general diagram of the operation of the AD7266 in
this mode.
PARTIAL POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required. Either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate and the ADC is then
powered down for a relatively long duration between these
bursts of several conversions. When the AD7266 is in partial
power-down, all analog circuitry is powered down except for
the on-chip reference and reference buffer.
0
1
10
14
LEADING ZERO, I.D. BIT + CONVERSION RESULT
CS
SCLK
D
OUT
A
D
OUT
B
To enter partial power-down, the conversion process must be
interrupted by bringing CS high anywhere after the second
falling edge of SCLK and before the 10
th
falling edge of SCLK, as
shown in Figure 9. Once CS has been brought high in this
window of SCLKs, the part enters partial power-down, the
conversion that was initiated by the falling edge of CS is
terminated, and D
OUT
A and D
OUT
B go back into three-state. If
CS is brought high before the second SCLK falling edge, the
part remains in normal mode and does not power down. This
avoids accidental power-down due to glitches on the CS line.
Figure 8. Normal Mode Operation
The conversion is initiated on the falling edge of CS, as
described in the Serial Interface section. To ensure that the part
remains fully powered up at all times, CS must remain low until
at least 10 SCLK falling edges have elapsed after the falling edge
of CS. If CS is brought high any time after the 10
th
SCLK falling
edge but before the 14
th
SCLK falling edge, the part remains
powered up but the conversion is terminated and D
OUT
A and
D
OUT
B go back into three-state. Fourteen serial clock cycles are
required to complete the conversion and access the conversion
result. The DOUT line does not return to three-state after 14
SCLK cycles have elapsed, but instead does so when CS is
brought high again. If CS is left low for another 2 SCLK cycles
(e.g. if only a 16 SCLK burst is available), two trailing zeros are
clocked out after the data. If CS is left low for a further 16 SCLK
cycles again, the result from the other ADC on board is also
0
1
2
10
14
CS
SCLK
TRI-STATE
D
OUT
A
D
OUT
B
Figure 9. Entering Partial Power-Down Mode
Rev. PrG | Page 13 of 17
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| AD7266BCPZ-REEL | 功能描述:IC ADC 12BIT 3CHAN 2MSPS 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端，單極 |
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