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參數(shù)資料
| 型號(hào)： | AD7273 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | 3MSPS,10-/12-Bit ADCs in 8-Lead TSOT |
| 中文描述： | 3MSPS，10-/12-Bit模數(shù)轉(zhuǎn)換器在8引腳TSOT |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 243K |
| 代理商： | AD7273 |
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PRELIMINARY TECHNICAL DATA
Preliminary Technical Data
AD7273/AD7274
CIRCUIT INFORMATION
The AD7273/AD7274 are high speed, low power, 10-/12-
Bit, single supply, analog-to-digital converters (ADC)
respectively. The parts can be operated from a +2.35V to
+3.6V supply. When operated from any supply voltage
within this range, the AD7273/AD7274 are capable of
throughput rates of 3 MSPS when provided with a 52
MHz clock.
The AD7273/AD7274 provide the user with an on-chip
track/hold, A/D converter, and a serial interface housed in
an 8-lead TSOT or an 8-lead MSOP package, which
offers the user considerable space saving advantages over
alternative solutions. The serial clock input accesses data
from the part but also provides the clock source for the
successive-approximation A/D converter. The analog
input range is 0 to V
REF
. An external reference is required
by the ADC and this reference can be in the range of 1.2V
to V
DD
.
The AD7273/AD7274 also feature a Power-Down option
to allow power saving between conversions. The power
down feature is implemented across the standard serial
interface as described in the Modes of Operation section.
CONVERTER OPERATION
The AD7273/AD7274 is a successive-approximation ana-
log-to-digital converter based around a charge redistribu-
tion DAC. Figures 7 and 8 show simplified schematics of
the ADC. Figure 7 shows the ADC during its acquisition
phase. SW2 is closed and SW1 is in position A, the com-
When the ADC starts a conversion, see Figure 8, SW2
will open and SW1 will move to position B causing the
comparator to become unbalanced. The Control Logic
and the Charge Redistribution DAC are used to add and
subtract fixed amounts of charge from the sampling ca-
pacitor to bring the comparator back into a balanced con-
dition. When the comparator is rebalanced the conversion
is complete. The Control Logic generates the ADC out-
put code. Figure 9 shows the ADC transfer function.
Figure 7. ADC Acquisition Phase
ADC TRANSFER FUNCTION
The output coding of the AD7273/AD7274 is straight
binary. The designed code transitions occur midway
between succesive integer LSB values, i.e, 0.5LSB,
1.5LSBs, etc. The LSB size is V
REF
/4096 for the AD7274,
V
REF
/1024 for the AD7273. The ideal transfer characteris-
tic for the AD7273/AD7274 is shown in Figure 9.
Figure 8. ADC Conversion Phase
CHARGE
REDISTRIBUTION
DAC
VIN
VDD / 2
SAMPLING
CAPACITOR
COMPARATOR
CONTROL
LOGIC
CONVERSION
PHASE
SW1
A
B
SW2
AGND
Figure 9. AD7273/AD7274 Transfer Characteristic
000...000
0V
A
ANALOG INPUT
111...111
111...110
000...001
000...010
111...000
011...111
0.5LSB
+VDD-1.5LSB
1LSB = VREF/1024 (AD7273)
1LSB = VREF/4096 (AD7274)
CHARGE
REDISTRIBUTION
DAC
VIN
VDD / 2
SAMPLING
CAPACITOR
COMPARATOR
CONTROL
LOGIC
ACQUISITION
PHASE
SW1
A
B
SW2
AGND
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