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| 型號(hào)： | AD7273BUJ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3MSPS,10-/12-Bit ADCs in 8-Lead TSOT |
| 中文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | MO-193BA, TSOT-8 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 243K |
| 代理商： | AD7273BUJ-REEL |
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PRELIMINARY TECHNICAL DATA
AD7273/AD7274
Preliminary Technical Data
Table II provides some typical performance data with
various op-amps used as the input buffer under the same
set-up conditions.
Op-amp in the AD7274 SNR Performance
input buffer
TBD kHz Input
AD8510
TBD dB
AD8610
TBD dB
AD8038 TBD dB
AD8519
TBD dB
When no amplifier is used to drive the analog input, the
source impedance should be limited to low values. The
maximum source impedance will depend on the amount
of total harmonic distortion (THD) that can be
tolerated. The THD will increase as the source
impedance increases and performance will degrade. See
TPC6.
Table II. AD7274 performance for various Input Buffers
Digital Inputs
The digital inputs applied to the AD7273/AD7274 are not
limited by the maximum ratings which limit the analog
inputs. Instead, the digitals inputs applied can go to TBD
V and are not restricted by the V
DD
+ 0.3V limit as on the
analog inputs. For example, if the AD7273/AD7274 were
operated with a V
DD
of 3V then 5V logic levels could be
used on the digital inputs. However, it is important to
note that the data output on SDATA will still have 3V
logic levels when V
DD
= 3V. Another advantage of SCLK
and
not being restricted by the V
DD
+ 0.3V limit is
the fact that power supply sequencing issues are avoided.
If
or SCLK are applied before V
DD
then there is no
risk of latch-up as there would be on the analog inputs if a
signal greater than 0.3V was applied prior to V
DD
.
MODES OF OPERATION
The mode of operation of the AD7273/AD7274 is se-
lected by controlling the logic state of the
during a conversion. There are two possible modes of
operation, Normal Mode and Power-Down Mode. The
point at which
is pulled high after the conversion has
been initiated will determine whether the AD7273/
AD7274 will enter Power-Down Mode or not. Similarly,
if already in Power-Down then
the device will return to Normal operation or remain in
Power-Down. These modes of operation are designed to
provide flexible power management options. These op-
tions can be chosen to optimize the power dissipation/
throughput rate ratio for different application
requirements.
Normal Mode
This mode is intended for fastest throughput rate perfor-
mance as the user does not have to worry about any
power-up times with the AD7273/AD7274 remaining fully
powered all the time. Figure 12 shows the general dia-
gram of the operation of the AD7273/AD7274 in this
mode.
The conversion is iniated on the falling edge of
described in the Serial Interface section. To ensure the
part remains fully powered up at all times
low until at least 10 SCLK falling edges have elapsed after
the falling edge of
. If
is brought high any time
after the 10th SCLK falling, the part will remain powered
up but the conversion
will be terminated and SDATA will
go back into three-state.
For the AD7274 a minimum of 14 serial clock cycles are
required to complete the conversion and access the
complete conversion result. For the AD7273 a minimum
of 12 serial clock cycles are required to complete the con-
version and access the complete conversion result.
may idle high until the next conversion or may idle
low until
returns high sometime prior to the next
conversion (effectively idling
Once a data transfer is complete (SDATA has returned to
three-state), another conversion can be initiated after the
quiet time, t
QUIET
, has elapsed by bringing
signal
can control whether
as
must remain
low).
low again.
Figure 12. Normal Mode Operation
12
14
16
AD7273/74
VALIDDATA
SDATA
SCLK
&6
1
10
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