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參數(shù)資料
型號： AD7274BUJZ-500RL7
廠商： Analog Devices Inc
文件頁數(shù)： 3/29頁
文件大?。?/td> 0K
描述： IC ADC 12BIT 3MSPS TSOT23-8
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 3M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 18mW
電壓電源： 單電源
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： SOT-23-8 薄型，TSOT-23-8
供應(yīng)商設(shè)備封裝： TSOT-23-8
包裝： 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型： 1 個單端，單極
其它名稱： AD7274BUJZ-500RL7DKR
AD7273/AD7274
Rev. 0 | Page 10 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD 1
SDATA
2
CS
3
AGND
4
VIN
8
DGND
7
SCLK
6
VREF
5
AD7273/
AD7274
TOP VIEW
(Not to Scale)
04973-008
Figure 8. 8-Lead MSOP Pin Configuration
VDD
VIN
1
SDATA
2
3
4
8
7
6
5
DGND
AGND
CS
SCLK
VREF
AD7273/
AD7274
TOP VIEW
(Not to Scale)
04973-009
Figure 9. 8-Lead TSOT Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
MSOP
TSOT
Mnemonic
Description
1
VDD
Power Supply Input. The VDD range for the AD7273/AD7274 is from 2.35 V to 3.6 V.
2
SDATA
Data Out. Logic output. The conversion result from the AD7273/AD7274 is provided on this output as a
serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from
the AD7274 consists of two leading zeros followed by the 12 bits of conversion data and two trailing
zeros, provided MSB first. The data stream from the AD7273 consists of two leading zeros followed
by the 10 bits of conversion data and four trailing zeros, provided MSB first.
3
7
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversion on
the AD7273/AD7274 and framing the serial data transfer.
4
8
AGND
Analog Ground. Ground reference point for all circuitry on the AD7273/AD7274. All analog signals
and any external reference signal should be referred to this AGND voltage.
5
VREF
Voltage Reference Input. This pin becomes the reference voltage input. An external reference should
be applied at this pin. The external reference input range is 1.4 V to VDD. A 10 μF capacitor should be
tied between this pin and AGND.
6
SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock
input is also used as the clock source for the conversion process of AD7273/AD7274.
7
3
DGND
Digital Ground. Ground reference point for all digital circuitry on the AD7273/AD7274. The DGND and
AGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even
on a transient basis.
8
4
VIN
Analog Input. Single-ended analog input channel. The input range is 0 to VREF.
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