參數(shù)資料
型號(hào)： AD7277
廠商： Analog Devices, Inc.
元件分類(lèi)： 串行ADC
英文描述： 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
中文描述： 3MSPS，12/10/8位ADC的6引腳TSOT
文件頁(yè)數(shù)： 16/20頁(yè)
文件大?。?/td> 255K
代理商： AD7277
–
16
–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7276/AD7277/AD7278
Preliminary Technical Data
Figure 13. Entering Power Down Mode
Figure 14. Exiting Power Down Mode
THREE-STATE
1
16
10
2
SDATA
SCLK
&6
INVALID DATA
SCLK
&6
INVALIDDATA
VALIDDATA
1
10
16
16
1
THE PARTBEGINS
TO POWER UP
THE PARTIS FULLY
POWEREDUPWITHVIN
FULLY ACQUIRED
A
SDATA
Power-Down Mode
This mode is intended for use in applications where
slower throughput rates are required; either the ADC is
powered down between each conversion, or a series of
conversions may be performed at a high throughput rate
and then the ADC is powered down for a relatively long
duration between these bursts of several conversions.
When the AD7276/AD7277/AD7278 is in Power-Down,
all analog circuitry is powered down.
To enter Power-Down, the conversion process must be
interrupted by bringing
high anywhere after the second
falling edge of SCLK and before the 10th falling edge of
SCLK as shown in Figure 13. Once
high in this window of SCLKs, then the part will enter
Power-Down and the conversion that was intiated by the
falling edge of
will be terminated and SDATA will go
back into three-state. If
is brought high before the
second SCLK falling edge, then the part will remain in
Normal Mode and will not power-down. This will avoid
accidental power-down due to glitches on the
has been brought
line.
In order to exit this mode of operation and power the
AD7276/AD7277/AD7278 up again, a dummy conversion
is performed. On the falling edge of
begin to power up, and will continue to power up as long
as
is held low until after the falling edge of the 10th
SCLK. The device will be fully powered up once 16
SCLKs have elapsed and valid data will result from the
next conversion as shown in Figure 14. If
high before the 10th falling edge of SCLK, then the
AD7276/AD7277/AD7278 will go back into Power-
Down again. This avoids accidental power up due to
glitches on the
line or an inadvertent burst of 8 SCLK
cycles while
is low. So, although the device may begin
to power up on the falling edge of
again on the rising edge of
the 10th SCLK falling edge.
the device will
is brought
, it will power down
as long as it occurs before
相關(guān)PDF資料
PDF描述
AD7277BRM 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
AD7277BUJ-REEL 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
AD7278 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
AD7278BRMJ 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
AD7278BUJ-REEL 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
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AD7277BRM 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
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