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參數(shù)資料
| 型號： | AD7277BRM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT |
| 中文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | MO-187AA, MSOP-8 |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 255K |
| 代理商： | AD7277BRM |
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18
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REV. PrF
PRELIMINARY TECHNICAL DATA
AD7276/AD7277/AD7278
SERIAL INTERFACE
Figures 16, 17 and 18 show the detailed timing diagram
for serial interfacing to the AD7276, AD7277 and
AD7278 respectively. The serial clock provides the
conversion clock and also controls the transfer of
information from the AD7276/AD7277/AD7278 during
conversion.
The
signal initiates the data transfer and conversion
process. The falling edge of
into hold mode, takes the bus out of three-state and the
analog input is sampled at this point. The conversion is
also initiated at this point.
For the AD7276 the conversion will require 14 SCLK
cycles to complete. Once 13 SCLK falling edges have
elapsed the track and hold will go back into track on the
next SCLK rising edge as shown in Figure 16 at point B.
If the rising edge of
occurs before 14 SCLKs have
elapsed then the conversion will be terminated and the
SDATA line will go back into three-state. If 16 SCLKs
are considered in the cycle, the last two bits will be zeros
and SDATA will return to three-state on the 16th SCLK
falling edge as shown in Figure 16.
For the AD7277 the conversion will require 12 SCLK
cycles to complete. Once 11 SCLK falling edges have
elapsed, the track and hold will go back into track on the
next SCLK rising edge, as shown in Figure 17 at point B.
If the rising edge of
occurs before 12 SCLKs have
elapsed then the conversion will be terminated and the
SDATA line will go back into three-state. If 16 SCLKs
are considered in the cycle, the AD7277 will clock out
four trailing zeros for the last four bits and SDATA will
return to three-state on the 16th SCLK falling edge, as
shown in Figure 17.
For the AD7278 the conversion will require 10 SCLK
cycles to complete. Once 9 SCLK falling edges have
Preliminary Technical Data
puts the track and hold
Figure 16. AD7276 Serial Interface Timing Diagram
elapsed, the track and hold will go back into track on the
next rising edge. If the rising edge of
SCLKs have elapsed then the part will enter Power-Down
mode. If 16 SCLKs are considered in the cycle, the
AD7278 will clock out six trailing zeros for the last six
bits and SDATA will return to three-state on the 16th
SCLK falling edge, as shown in Figure 18.
If the user considers a 14 SCLKs cycle serial interface for
the AD7276/AD7277/AD7278,
high after the 14th SCLK falling edge, the last two
trailing zeros will be ignored and SDATA will go back
into three-state. In this case, the 3MSPS throughput could
be achieved using a 45MHz clock frequency.
going low clocks out the first leading zero to be read
in by the microcontroller or DSP. The remaining data is
then clocked out by subsequent SCLK falling edges
beginning with the 2nd leading zero. Thus the first falling
clock edge on the serial clock has the first leading zero
provided and also clocks out the second leading zero. The
final bit in the data transfer is valid on the 16th falling
edge, having being clocked out on the previous (15th)
falling edge.
In applications with a slower SCLK, it is possible to read
in data on each SCLK rising edge. In that case, the first
falling edge of SCLK will clock out the second leading
zero and it could be read in the first rising edge. However,
the first leading zero that was clocked out when
low will be missed unless it was not read in the first falling
edge. The 15th falling edge of SCLK will clock out the
last bit and it could be read in the 15th rising SCLK edge.
If
goes low just after one the SCLK falling edge has
elapsed,
will clock out the first leading zero as before
and it may be read in the SCLK rising edge. The next
SCLK falling edge will clock out the second leading zero
and it could be read in the following rising edge.
occurs before 10
needs to be brought
went
&6
SCLK
1
5
13
15
SDATA
2 LEADING
ZERO
’
S
THREE-
STATE
t
4
2
3
4
16
t
5
t
3
t
quiet
t
convert
t
2
THREE-STATE
DB10
t
6
t
7
t
8
14
ZERO
Z
B
t
1
1/ THROUGHPUT
DB11
DB9
ZERO
ZERO
DB0
DB1
2 TRAILING
ZERO
’
S
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