參數(shù)資料
型號: AD7277BRM
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
中文描述: 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝: MO-187AA, MSOP-8
文件頁數(shù): 6/20頁
文件大?。?/td> 255K
代理商: AD7277BRM
6
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7276/AD7277/AD7278
Preliminary Technical Data
Figure 5. AD7276 Serial Interface Timing Diagram
Timing Example 1
From Figure 6, having f
SCLK
= 52 MHz and a throughput of 3MSPS, gives a cycle time of t
2
+ 12.5(1/f
SCLK
) + t
ACQ
=
333 ns. With t
2
= TBD ns min, this leaves t
ACQ
to be TBD ns. This TBD ns satisfies the requirement of TBD ns for
t
ACQ
. Figure 6 shows that, t
ACQ
comprises of 2.5(1/f
SCLK
) + t
8
+ t
QUIET
, where t
8
= TBD ns max. This allows a value of
TBD ns for t
QUIET
satisfying the minimum requirement of TBD ns.
Timing Example 2
Having f
SCLK
= 20 MHz and a throughput of 1.5 MSPS, gives a cycle time of t
2
+ 12.5(1/f
SCLK
) + t
ACQ
= 666 ns.
With t
2
= TBD ns min, this leaves t
ACQ
to be TBD ns. This TBD ns satisfies the requirement of TBD ns for t
ACQ
. From
Figure 6, t
ACQ
comprises of 2.5(1/f
SCLK
) + t
8
+ t
QUIET
, where t
8
= TBD ns max. This allows a values of TBD ns for
t
QUIET
satisfying the minimum requirement of TBD ns.
Figure 6. Serial Interface Timing Example
Figures 5 and 6 show some of the timing parameters from the Timing Specifications table.
&6
SCLK
1
5
13
15
SDATA
2 LEADING
ZERO’S
THREE-
STATE
t
4
2
3
4
16
t
5
t
3
t
quiet
t
convert
t
2
THREE-STATE
DB10
t
6
t
7
t
8
14
ZERO
Z
B
t
1
1/ THROUGHPUT
DB11
DB9
ZERO
ZERO
DB0
DB1
2 TRAILING
ZERO’S
SCLK
1
5
2
3
4
&6
13
t
quiet
t
2
t
8
14
B
t
acquisition
12.5(1/fSCLK)
1/THROUGHPUT
t
convert
t
1
15
16
12
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