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參數(shù)資料
| 型號： | AD7298BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/25頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SPI/SRL 1M 20LFCSP |
| 特色產(chǎn)品： | AD7298 ADC with Temperature Sensor |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 22.7mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-WQ（4x4） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 8 個單端，單極 |
AD7298
Rev. B | Page 20 of 24
Full Power-Down Mode
In this mode, all internal circuitry on the AD7298 is powered
down and no information is retained in the control register or any
other internal register. If the averaging feature for the tempera-
ture sensor is enabled in the control register (TSENSEAVG), the
averaging is reset once the device enters power-down mode.
The AD7298 is placed into full power-down mode by bringing
the logic level on the PD/RST pin low for greater than 100 ns.
When placing the AD7298 in full power-down mode, the ADC
inputs must return to 0 V. The PD/RST pin is asynchronous to
the clock, thus it can be triggered at any time. The part can be
powered up for normal operation by bringing the PD/RST pin
logic level back to a high logic state.
The full power-down feature can be used to reduce the average
power consumed by the AD7298 when operating at lower
throughput rates. The user should ensure that tPOWER_UP has
elapsed prior to programming the control register and initiating
a valid conversion.
POWERING UP THE AD7298
The AD7298 contains a power-on reset circuit, which sets
the control register to its default setting of all zeros, thus the
internal reference is enabled and the device is configured for the
normal mode of operation. On power-up, the internal reference
is by default enabled, which takes up 6 ms (maximum) to
power-up.
If an external reference is being used, the user does not need to
wait for the internal reference to power-up fully. The AD7298
digital interface is fully functional after 500 μs from initial
power-up. Therefore, the user can write to the control register
after 500 μs to switch to external reference mode. The AD7298
is then immediately ready to convert once the external reference
is available on the VREF pin.
When supplies are first applied to the AD7298, the user must
wait the specified 500 μs before programming the control
register to select the desired channels for conversion.
RESET
The AD7298 includes a reset feature that can be used to reset
the device and the contents of all internal registers, including
the control register, to their default state.
To activate the reset operation, the PD/RST pin should be
brought low for no longer than 100 ns. It is asynchronous with
the clock, thus it can be triggered at any time. If the PD/RST pin
is held low for greater than 100 ns, the part enters full power-
down mode. It is imperative that the PD/RST pin be held at a
stable logic level at all times to ensure normal operation.
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