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| 型號(hào)： | AD7305 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
| 中文描述： | 3伏/ 5伏，軌至軌四路，8位DAC |
| 文件頁(yè)數(shù)： | 5/14頁(yè) |
| 文件大?。?/td> | 936K |
| 代理商： | AD7305 |
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–
5
–
AD7304/AD7305
REV. A
Table III. AD7305 Control Logic Truth Table
WR
A1
A0
LDAC
Input Register Function
DAC Register Function
L
↑
+
L
↑
+
L
↑
+
L
↑
+
H
L
H
H
L
L
L
L
H
H
H
H
X
X
X
X
L
L
H
H
L
L
H
H
X
X
X
X
H
H
H
H
H
H
H
H
L
L
↑
+
H
REG A Loaded with DB0–DB7
REG A Latched with DB0–DB7
REG B Loaded with DB0–DB7
REG B Latched with DB0–DB7
REG C Loaded with DB0–DB7
REG C Latched with DB0–DB7
REG D Loaded with DB0–DB7
REG D Latched with DB0–DB7
No Effect
Input REG x Transparent to DB0–DB7
No Effect
No Effect, Device Not Selected
Latched with Previous Contents, No Change
Latched with Previous Contents, No Change
Latched with Previous Contents, No Change
Latched with Previous Contents, No Change
Latched with Previous Contents, No Change
Latched with Previous Contents, No Change
Latched with Previous Contents, No Change
Latched with Previous Contents, No Change
All Input Register Contents Loaded, Register Transparent
Register Transparent
All Input Register Contents Latched
No Effect, Device Not Selected
NOTES
1
↑
+ positive logic transition;
↓
– negative logic transition; X Don’t Care.
2
LDAC
is a level sensitive input.
PIN CONFIGURATIONS
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
V
OUT
B
V
OUT
A
V
SS
V
REF
B
V
REF
A
GND
LDAC
CLR
V
OUT
C
V
OUT
D
V
DD
V
REF
C
V
REF
D
SDI/SHDN
CLK
CS
AD7304
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
AD7305
DB5
DB6
V
OUT
A
V
SS
V
REF
DB7
LDAC
GND
DB2
DB1
V
OUT
D
V
DD
A0/SHDN
DB0
WR
A1
V
OUT
B
V
OUT
C
DB4
DB3
t
AH
t
DH
t
LH
t
LDW
t
WR
t
AS
t
DS
t
LS
t
S
ERR1 LSB
A0, A1
WR
D0
–
D7
LDAC
V
OUT
Figure 4. AD7305 Timing Diagram
t
SDR
A0/SHDN
I
DD
t
SDN
Figure 5. AD7305 Timing Diagram
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