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| 型號： | AD7305BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | +3 V/+5 V, Rail-to-Rail Quad, 8-Bit DAC |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 1 us SETTLING TIME, 8-BIT DAC, PDSO20 |
| 封裝： | MS-013AC, SOIC-20 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 936K |
| 代理商： | AD7305BR |
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD7304/AD7305*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1998
FUNCTIONAL BLOCK DIAGRAMS
PWR ON
RESET
V
SS
AD7304
V
OUT
A
V
OUT
B
INPUT
REG A
DAC A
CS
LDAC
SDI/SHDN
GND
CLK
8
8
8
8
DAC A
REG
DAC B
DAC B
REG
INPUT
REG B
8
INPUT
REG C
8
8
8
8
DAC C
REG
DAC D
DAC D
REG
INPUT
REG D
DAC C
SERIAL
REG
V
REF
B V
REF
A
V
OUT
C
V
OUT
D
CLR
V
REF
C V
REF
D
V
DD
PWR ON
RESET
V
SS
V
OUT
A
V
OUT
B
INPUT
REG A
DAC A
WR
LDAC
A0/SHDN
GND
A1
8
8
8
8
DAC A
REG
DAC B
DAC B
REG
8
8
8
8
8
DAC C
REG
DAC D
DAC D
REG
DAC C
V
REF
V
OUT
C
V
OUT
D
V
DD
INPUT
REG B
INPUT
REG C
INPUT
REG D
DECODE
DB0
DB1
DB2
DB3
DB4
DB5
DB6
AD7305
FEATURES
Four 8-Bit DACs in One Package
+3 V, +5 V and 5 V Operation
Rail-to-Rail REF-Input to Voltage Output Swing
2.6 MHz Reference Multiplying Bandwidth
Compact 1.1 mm Height TSSOP 16-/20-Lead Package
Internal Power ON Reset
SPI Serial Interface Compatible—AD7304
Fast Parallel Interface—AD7305
40 A Power Shutdown
APPLICATIONS
Automotive Output Span Voltage
Instrumentation, Digitally Controlled Calibration
Pin-Compatible AD7226 Replacement when V
DD
< 5.5 V
GENERAL DESCRIPTION
The AD7304/AD7305 are quad, 8-bit DACs that operate from a
single +3 V to +5 V supply or
±
5 V supplies. The AD7304 has a
serial interface, while the AD7305 has a parallel interface. Inter-
nal precision buffers swing rail-to-rail. The reference input range
includes both supply rails allowing for positive or negative full-
scale output voltages. Operation is guaranteed over the supply
voltage range of +2.7 V to +5.5 V, consuming less than 9 mW
from a +3 V supply.
The full-scale voltage output is determined by the external refer-
ence input voltage applied. The rail-to-rail V
REF
input to DAC
V
OUT
allows for a full-scale voltage set equal the positive supply
V
DD
, the negative supply V
SS
or any value in between.
The AD7304’s doubled-buffered serial-data interface offers high
speed, three-wire, SPI and microcontroller compatible inputs
using data in (SDI), clock (CLK) and chip select (
CS
) pins.
Additionally, an internal power-on reset sets the output to zero
scale.
The parallel input AD7305 uses a standard address decode
along with the
WR
control line to load data into the input regis-
ters. The double buffered architecture allows all four input
registers to be preloaded with new values, followed by a
LDAC
control strobe which copies all the new data into the DAC regis-
ters thereby updating the analog output values. When operating
from less than +5.5 V, the AD7305 is pin-compatible with the
popular industry standard AD7226.
An internal power ON reset places both parts in the zero-scale
state at turn ON. A 40
μ
A power shutdown (SHDN) feature is
activated on both parts by tristating the SDI/SHDN pin on the
AD7304, and tristating the A0/SHDN address pin on the
AD7305.
The AD7304/AD7305 are specified over the extended industrial
(–40
°
C to +85
°
C), and the automotive (–40
°
C to +125
°
C)
temperature ranges. AD7304s are available in 16-lead plastic
DIP (N-16), and wide-body SOL-16 (R-16) packages. The
parallel input AD7305 is available in the 20-lead plastic DIP
(N-20), and the SOL-20 (R-20) surface mount package. For
ultracompact applications the thin 1.1 mm TSSOP-16 (RU-16)
package will be available for the AD7304, while the TSSOP-20
(RU-20) will house the AD7305.
*
Protected under Patent Number 5684481.
+3 V/+5 V, Rail-to-Rail
Quad, 8-Bit DAC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7305BRU | +3 V/+5 V, Rail-to-Rail Quad, 8-Bit DAC |
| AD7305* | Ultra High Speed Operational Amplifier; Package: SO; No of Pins: 8; Temperature Range: 0°C to +70°C |
| AD7306 | 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors |
| AD7306AN | 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors |
| AD7306AR | ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75% |
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| AD7305BR-REEL | 功能描述:IC DAC 8BIT QUAD R-R 20-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色產(chǎn)品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 標準包裝:91 系列:- 設(shè)置時間:4µs 位數(shù):10 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:8 電壓電源:單電源 功率耗散（最大）:2.7mW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:14-DFN-EP（4x3） 包裝:管件 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD7305BR-REEL7 | 功能描述:INTEGRATED CIRCUIT 制造商:analog devices inc. 系列:* 包裝:帶卷（TR） 零件狀態(tài):最後搶購 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 供應(yīng)商器件封裝:20-SOIC 標準包裝:1 |
| AD7305BRU | 功能描述:IC DAC 8BIT QUAD R-R 20-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標準包裝:47 系列:- 設(shè)置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
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| AD7305BRUZ | 功能描述:IC DAC 8BIT QUAD R-R 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
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