參數(shù)資料
型號(hào)： AD7327BRUZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 26/37頁(yè)
文件大小： 0K
描述： IC ADC 12BIT+SAR 8CHAN 20-TSSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 12
采樣率（每秒）： 500k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 17mW
電壓電源： 雙 ±
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)差分，單極；4 個(gè)差分，雙極
配用： EVAL-AD7327CBZ-ND - BOARD EVALUATION FOR AD7327
Data Sheet
AD7327
Rev. B | Page 31 of 36
SERIAL INTERFACE
Figure 53 shows the timing diagram for the serial interface of
the AD7327. The serial clock applied to the SCLK pin provides
the conversion clock and controls the transfer of information to
and from the AD7327 during a conversion.
The CS signal initiates the data transfer and the conversion
process. The falling edge of CS puts the track-and-hold into
hold mode and takes the bus out of three-state. Then the analog
input signal is sampled. Once the conversion is initiated, it requires
16 SCLK cycles to complete.
The track-and-hold goes back into track mode on the 14th SCLK
rising edge. On the 16th SCLK falling edge, the DOUT line returns
to three-state. If the rising edge of CS occurs before 16 SCLK
cycles have elapsed, the conversion is terminated, and the DOUT
line returns to three-state. Depending on where the CS signal is
brought high, the addressed register may be updated.
Data is clocked into the AD7327 on the SCLK falling edge. The
three MSBs on the DIN line are decoded to select which register
is addressed. The control register is a 12-bit register. If the control
register is addressed by the three MSBs, the data on the DIN
line is loaded into the control on the 15th SCLK falling edge. If
the sequence register or either of the range registers is addressed,
the data on the DIN line is loaded into the addressed register
on the 11th SCLK falling edge.
Conversion data is clocked out of the AD7327 on each SCLK
falling edge. Data on the DOUT line consists of three channel
identifier bits, a sign bit, and a 12-bit conversion result. The
channel identifier bits are used to indicate which channel
corresponds to the conversion result. The ADD2 bit is clocked
out on the CS falling edge, and the ADD1 bit is clocked out on
the first SCLK falling edge.
ADD1
1
2
3
4
5
13
14
15
16
WRITE
REG
SEL1
REG
SEL2
LSB
MSB
ADD0
SIGN
DB11
DB10
DB2
DB1
DB0
t2
t6
t4
t9
t10
t3
t7
t5
t8
t1
tQUIET
tCONVERT
SCLK
CS
DOUT
THREE-
STATE
THREE-STATE
DIN
ADD2
3 IDENTIFICATION BITS
05401-
036
DON’T
CARE
Figure 53. Serial Interface Timing Diagram (Control Register Write)
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