t1 t2 t
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AD73311ARZ
寤犲晢锛� Analog Devices Inc
鏂囦欢闋佹暩(sh霉)锛� 34/36闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC PROCESSOR FRONT END LP 20SOIC
妯欐簴鍖呰锛� 37
浣嶆暩(sh霉)锛� 16
閫氶亾鏁�(sh霉)锛� 2
鍔熺巼锛堢摝鐗癸級锛� 50mW
闆诲 - 闆绘簮锛屾ā鎿細 3V
闆诲 - 闆绘簮锛屾暩(sh霉)瀛楋細 3V
灏佽/澶栨锛� 20-SOIC锛�0.295"锛�7.50mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 20-SOIC W
鍖呰锛� 绠′欢
鐢�(ch菐n)鍝佺洰閷勯爜闈細 799 (CN2011-ZH PDF)
AD73311
鈥�7鈥�
REV. B
t1
t2
t3
Figure 1. MCLK Timing
TIMING CHARACTERISTICS
Limit at
Parameter
TA = 鈥�40 C to +85 C
Unit
Description
Clock Signals
See Figure 1
t1
61
ns min
MCLK Period
t2
24.4
ns min
MCLK Width High
t3
24.4
ns min
MCLK Width Low
Serial Port
See Figures 3 and 4
t4
t1
ns min
SCLK Period
t5
0.4
脳 t1
ns min
SCLK Width High
t6
0.4
脳 t1
ns min
SCLK Width Low
t7
20
ns typ
SDI/SDIFS Setup Before SCLK Low
t8
0
ns typ
SDI/SDIFS Hold After SCLK Low
t9
10
ns typ
SDOFS Delay from SCLK High
t10
10
ns typ
SDOFS Hold After SCLK High
t11
10
ns typ
SDO Hold After SCLK High
t12
10
ns typ
SDO Delay from SCLK High
t13
30
ns typ
SCLK Delay from MCLK
(AVDD = +5 V
10%; DVDD = +5 V
10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless
otherwise noted)
100 AIOL
100 AIOH
CL
15pF
+2.1V
TO OUTPUT
PIN
Figure 2. Load Circuit for Timing Specifications
t1
t2
t3
t13
t5
t6
t4
MCLK
SCLK
*
SCLK IS INDIVIDUALLY PROGRAMMABLE
IN FREQUENCY (MCLK/4 SHOWN HERE).
*
Figure 3. SCLK Timing
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
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AD73311ARZ-REEL 鍔熻兘鎻忚堪:IC PROCESSOR FRONT END LP 20SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃摤鍓嶇 (AFE) 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯欐簴鍖呰:2,500 绯诲垪:- 浣嶆暩(sh霉):- 閫氶亾鏁�(sh霉):2 鍔熺巼锛堢摝鐗癸級:- 闆诲 - 闆绘簮锛屾ā鎿�:3 V ~ 3.6 V 闆诲 - 闆绘簮锛屾暩(sh霉)瀛�:3 V ~ 3.6 V 灏佽/澶栨:32-VFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:32-QFN锛�5x5锛� 鍖呰:甯跺嵎 (TR)
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