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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | AD73311LARSZ |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 31/36闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC PROCESSOR FRONT END LP 20SSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 66 |
| 浣嶆暩(sh霉)锛� | 16 |
| 閫氶亾鏁�(sh霉)锛� | 2 |
| 鍔熺巼锛堢摝鐗癸級锛� | 50mW |
| 闆诲 - 闆绘簮锛屾ā鎿細 | 3V |
| 闆诲 - 闆绘簮锛屾暩(sh霉)瀛楋細 | 3V |
| 灏佽/澶栨锛� | 20-SSOP锛�0.209"锛�5.30mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 20-SSOP |
| 鍖呰锛� | 绠′欢 |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)绗�22闋�(y猫)绗�23闋�(y猫)绗�24闋�(y猫)绗�25闋�(y猫)绗�26闋�(y猫)绗�27闋�(y猫)绗�28闋�(y猫)绗�29闋�(y猫)绗�30闋�(y猫)鐣�(d膩ng)鍓嶇31闋�(y猫)绗�32闋�(y猫)绗�33闋�(y猫)绗�34闋�(y猫)绗�35闋�(y猫)绗�36闋�(y猫)
(AVDD = +5 V
10%; DVDD = +5 V
10%; DGND = AGND = 0 V, fMCLK = 16.384 MHz,
FS = 64 kHz; TA = TMIN to TMAX, unless otherwise noted)
AD73311A
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REFERENCE
REFCAP
Absolute Voltage, VREFCAP
1.2
V
5VEN = 0
2.4
V
5VEN = 1
REFCAP TC
50
ppm/
掳C 0.1 F Capacitor Required from
REFOUT
REFCAP to AGND2
Typical Output Impedance
68
Absolute Voltage, VREFOUT
1.2
V
5VEN = 0, Unloaded
2.4
V
5VEN = 1, Unloaded
Minimum Load Resistance
2
k
5VEN = 1
Maximum Load Capacitance
100
pF
ADC SPECIFICATIONS
Maximum Input Range at VIN
2, 3
3.156
V p-p
5VEN = 1, Measured Differentially
3.17
dBm
Nominal Reference Level at VIN
2.1908
V p-p
5VEN = 1, Measured Differentially
(0 dBm0)
0
dBm
Absolute Gain
PGA = 0 dB
0.1
dB
1.0 kHz, 0 dBm0
PGA = 38 dB
鈥�0.5
dB
1.0 kHz, 0 dBm0
Gain Tracking Error
卤0.1
dB
1.0 kHz, +3 dBm0 to 鈥�50 dBm0
Signal to (Noise + Distortion)
Refer to Figure 5
PGA = 0 dB
76
dB
300 Hz to 3.4 kHz Frequency Range
59
dB
0 Hz to 32 kHz Frequency Range
PGA = 38 dB
71
dB
300 Hz to 3.4 kHz Frequency Range
57
dB
0 Hz to 32 kHz Frequency Range
Total Harmonic Distortion
PGA = 0 dB
鈥�76
dB
PGA = 38 dB
鈥�69
dB
Intermodulation Distortion
鈥�69
dB
PGA = 0 dB
Idle Channel Noise
鈥�67
dBm0
PGA = 0 dB
Crosstalk
鈥�80
dB
ADC Input Signal Level: 1.0 kHz, 0 dBm0
DAC Input at Idle
DC Offset
+20
mV
PGA = 0 dB
Power Supply Rejection
鈥�55
dB
Input Signal Level at AVDD and DVDD
Pins 1.0 kHz, 100 mV p-p Sine Wave
Group Delay
4, 5
25
s
64 kHz Output Sample Rate
Input Resistance at VIN
2, 4
25
k
6
DMCLK = 16.384 MHz
DAC SPECIFICATIONS
Maximum Voltage Output Swing
2
Single Ended
3.156
V p-p
5VEN = 1, PGA = 6 dB
3.17
dBm
Differential
6.312
V p-p
5VEN = 1, PGA = 6 dB
9.19
dBm
Nominal Voltage Output Swing (0 dBm0)
Single-Ended
2.1908
V p-p
5VEN = 1, PGA = 6 dB
0
dBm
Differential
4.3918
V p-p
5VEN = 1, PGA = 6 dB
6.02
dBm
Output Bias Voltage
VREFOUT
V typ
5VEN = 1, REFOUT Unloaded
Absolute Gain
卤0.4
dB
1.0 kHz, 0 dBm0
Gain Tracking Error
卤0.1
dB
1.0 kHz, +3 dBm0 to 鈥�50 dBm0
Signal to (Noise + Distortion)
Refer to Figure 5
PGA = 0 dB
66
dB
300 Hz to 3.4 kHz Frequency Range
64
dB
0 Hz to 32 kHz Frequency Range
PGA = 6 dB
66
dB
300 Hz to 3.4 kHz Frequency Range
64
dB
0 Hz to 32 kHz Frequency Range
Total Harmonic Distortion
PGA = 0 dB
鈥�62.5
dB
PGA = 6 dB
鈥�62.5
dB
Intermodulation Distortion
鈥�60
dB
PGA = 0
Idle Channel Noise
鈥�75
dBm0
PGA = 0
Crosstalk
鈥�80
dB
ADC Input Signal Level: AGND; DAC
Output Signal Level: 1.0 kHz, 0 dBm0
AD73311鈥揝PECIFICATIONS1
鈥�4鈥�
REV. B
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| AD73311LARSZ-REEL | 鍔熻兘鎻忚堪:IC PROCESSOR FRONT END LP 20SSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃摤鍓嶇 (AFE) 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:2,500 绯诲垪:- 浣嶆暩(sh霉):- 閫氶亾鏁�(sh霉):2 鍔熺巼锛堢摝鐗癸級:- 闆诲 - 闆绘簮锛屾ā鎿�:3 V ~ 3.6 V 闆诲 - 闆绘簮锛屾暩(sh霉)瀛�:3 V ~ 3.6 V 灏佽/澶栨:32-VFQFN 瑁搁湶鐒婄洡(p谩n) 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:32-QFN锛�5x5锛� 鍖呰:甯跺嵎 (TR) |
| AD73311LARSZ-REEL7 | 鍔熻兘鎻忚堪:IC PROCESSOR FRONT END LP 20SSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃摤鍓嶇 (AFE) 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:2,500 绯诲垪:- 浣嶆暩(sh霉):- 閫氶亾鏁�(sh霉):2 鍔熺巼锛堢摝鐗癸級:- 闆诲 - 闆绘簮锛屾ā鎿�:3 V ~ 3.6 V 闆诲 - 闆绘簮锛屾暩(sh霉)瀛�:3 V ~ 3.6 V 灏佽/澶栨:32-VFQFN 瑁搁湶鐒婄洡(p谩n) 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:32-QFN锛�5x5锛� 鍖呰:甯跺嵎 (TR) |
| AD73311LARU | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin TSSOP |
| AD73311LARU-REEL | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin TSSOP T/R |
| AD73311LARU-REEL7 | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin TSSOP T/R |
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