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參數(shù)資料
| 型號： | AD7393AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | +3 V, Parallel Input Micropower 10- and 12-Bit DACs |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 70 us SETTLING TIME, 10-BIT DAC, PDSO20 |
| 封裝： | MS-013AC, SOIC-20 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 199K |
| 代理商： | AD7393AR |
AD7392/AD7393
–9–
REV. A
RESET (
RS
) PIN
Forcing the asynchronous
RS
pin low will set the DAC register
to all zeros and the DAC output voltage will be zero volts. The
reset function is useful for setting the DAC outputs to zero at
power-up or after a power supply interruption. Test systems and
motor controllers are two of many applications that benefit from
powering up to a known state. The external reset pulse can be
generated by the microprocessor’s power-on RESET signal, by
an output from the microprocessor or by an external resistor
and capacitor. RESET has a Schmitt trigger input which results
in a clean reset function when using external resistor/capacitor
generated pulses. See the Control-Logic Truth Table I.
POWER SHUTDOWN (
SHDN
)
Maximum power savings can be achieved by using the power
shutdown control function. This hardware activated feature is
controlled by the active low input
SHDN
pin. This pin has a
Schmitt trigger input that helps desensitize it to slowly changing
inputs. By placing a logic low on this pin, the internal consump-
tion of the AD7392 or AD7393 is reduced to nanoamp levels,
guaranteed to 1.5
μ
A maximum over the operating temperature
range. If power is present at all times on the V
DD
pin while in
the shutdown mode, the internal DAC register will retain the
last programmed data value. The digital interface is still active
in shutdown, so that code changes can be made that will pro-
duce new DAC settings when the device is taken out of shut-
down. This data will be used when the part is returned to the
normal active state by placing the DAC back to its programmed
voltage setting. Figure 23 shows a plot of shutdown recovery
time with both I
DD
and V
OUT
displayed. In the shutdown state
the DAC output amplifier exhibits an open-circuit high resis-
tance state. Any load connected will stabilize at its termination
voltage. If the power shutdown feature is not needed, the user
should tie the
SHDN
pin to the V
DD
voltage thereby disabling
this function.
INPUT LOGIC LEVELS
All digital inputs are protected with a Zener-type ESD protec-
tion structure (Figure 28) that allows logic input voltages to
exceed the V
DD
supply voltage. This feature can be useful if the
user is driving one or more of the digital inputs with a 5 V
CMOS logic input-voltage level while operating the AD7392/
AD7393 on a +3 V power supply. If this mode of interface is
used, make sure that the V
OL
of the 5 V CMOS meets the V
IL
input requirement of the AD7392/AD7393 operating at 3 V.
See Figure 12 for a graph for digital logic input threshold versus
operating V
DD
supply voltage.
V
DD
LOGIC
IN
GND
1k
V
Figure 28. Equivalent Digital Input ESD Protection
In order to minimize power dissipation from input-logic levels
that are near the V
IH
and V
IL
logic input voltage specifications, a
Schmitt trigger design was used that minimizes the input-buffer
current consumption compared to traditional CMOS input
stages. Figure 11 shows a plot of incremental input voltage
versus supply current, showing that negligible current consump-
tion takes place when logic levels are in their quiescent state.
The normal cross over current still occurs during logic transi-
tions. A secondary advantage of this Schmitt trigger is the pre-
vention of false triggers that would occur with slow moving logic
transitions when a standard CMOS logic interface or opto-
isolators are used. The logic inputs DB11–DB0,
CS
,
RS
,
SHDN
all contain the Schmitt trigger circuits.
DIGITAL INTERFACE
The AD7392/AD7393 have a parallel data input. A functional
block diagram of the digital section is shown in Figure 4, while
Table I contains the truth table for the logic control inputs.
The chip select (
CS
) pin controls loading of data from the data
inputs on pins DB11–DB0. This active low input places the
input register into a transparent state allowing the data inputs to
directly change the DAC ladder values. When
CS
returns to
logic high within the data setup and hold time specifications, the
new value of data in the input-register will be latched. See Truth
Table for complete set of conditions.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7393ARU | 制造商:AD 制造商全稱:Analog Devices 功能描述:+3 V, Parallel Input Micropower 10- and 12-Bit DACs |
| ad7393aru-reel | 制造商:Rochester Electronics LLC 功能描述:10-BIT +3V TO +5V UPOWER DAC, PARALLEL - Tape and Reel 制造商:Analog Devices 功能描述: |
| AD7393ARZ | 制造商:Analog Devices 功能描述:DAC 1-CH R-2R 10-bit 20-Pin SOIC W |
| AD7394 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V, Dual, Serial Input 12-/10-Bit DACs |
| AD7394AN | 制造商:Rochester Electronics LLC 功能描述:X2, 12-BIT, +3V UPWR DAC - Bulk 制造商:Analog Devices 功能描述:IC 12BIT DAC 7394 DIP14 |
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