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參數(shù)資料
| 型號： | AD7441BRTZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT W/DIFF INP SOT-23-8 |
| 標準包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 9.25mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應商設備封裝： | SOT-23-8 |
| 包裝： | 標準包裝 |
| 輸入數(shù)目和類型： | 1 個偽差分，單極 |
| 其它名稱： | AD7441BRTZ-REEL7DKR |
AD7441/AD7451
Rev. D | Page 21 of 24
AD7441/AD7451 to DSP56xxx
The timer registers, for example, are loaded with a value that
provides an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and, there-
fore, the reading of data. The frequency of the serial clock is set
in the SCLKDIV register. When the instruction to transmit with
TFS is given, that is, AX0 = TX0, the state of the SCLK is checked.
The DSP waits until the SCLK has gone high, low, and high
before starting transmission. If the timer and SCLK values are
chosen such that the instruction to transmit occurs on or near
the rising edge of SCLK, then the data can either be transmitted
or wait until the next clock edge.
The connection diagram in Figure 35 shows how the AD7441/
AD7451 can be connected to the SSI (synchronous serial interface)
of the DSP56xxx family of DSPs from Motorola. The SSI is
operated in synchronous mode (SYN bit in CRB = 1) with
internally generated 1-bit clock period frame sync for both Tx
and Rx (Bit FSL1 = 1 and Bit FSL0 = 0 in CRB). Set the word
length to 16 by setting Bit WL1 = 1 and Bit WL0 = 0 in CRA. To
implement the power-down mode on the AD7441/AD7451, the
word length can be changed to eight bits by setting B it WL1 = 0
and Bit WL0 = 0 in CRA. Note that for signal processing applica-
tions, the frame synchronization signal from the DSP56xxx must
provide equidistant sampling.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value of 3,
an SCLK of 2 MHz is obtained and eight master clock periods
elapse for every one SCLK period. If the timer registers are
loaded with the value 803, 100.5 SCLKs occur between inter-
rupts and subsequently between transmit instructions. This
situation results in nonequidistant sampling, because the
transmit instruction occurs on an SCLK edge. If the number
of SCLKs between interrupts is a whole integer figure of N,
equidistant sampling is implemented by the DSP.
AD7441/
AD7451*
DSP56xxx*
SCLK
SRD
SR2
SCLK
SDATA
CS
*ADDITIONAL PINS REMOVED FOR CLARITY.
03
15
3-
0
35
Figure 35. Interfacing to the DSP56xxx
AD7441/AD7451 to TMS320C5x/C54x
The serial interface on the TMS320C5x/C54x uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices such as the
AD7441/AD7451. The CS input allows easy interfacing between
the TMS320C5x/C54x and the AD7441/AD7451 without any
glue logic required. The serial port of the TMS320C5x/C54x is
set up to operate in burst mode with internal CLKx (Tx serial
clock) and FSx (Tx frame sync). The serial port control register
(SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1,
and TXM = 1. The format bit, FO, can be set to 1 to set the word
length to eight bits in order to implement the power-down
mode on the AD7441/AD7451. The connection diagram is
shown in
. Note that for signal processing applications,
the frame synchronization signal from the TMS320C5x/ C54x
must provide equidistant sampling.
AD7441/
AD7451*
TMS320C5x/
C54x*
CLKx
DR
FSx
FSR
SCLK
CS
CLKR
*ADDITIONAL PINS REMOVED FOR CLARITY.
03
15
3-
0
34
Figure 34. Interfacing to the TMS320C5x/C54x
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