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參數(shù)資料
| 型號： | AD7441BRTZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/25頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT W/DIFF INP SOT-23-8 |
| 標準包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 9.25mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 標準包裝 |
| 輸入數(shù)目和類型： | 1 個偽差分，單極 |
| 其它名稱： | AD7441BRTZ-REEL7DKR |
AD7441/AD7451
Rev. D | Page 15 of 24
When no amplifier is used to drive the analog input, it is
recommended that the source impedance be limited to low
values. The maximum source impedance depends on the
amount of total harmonic distortion that can be tolerated.
The THD increases as the source impedance increases and
performance degrades.
Figure 25 shows a graph of THD vs. analog input signal
frequency for different source impedances.
0
–100
–90
–80
–70
–60
–50
–40
–30
–10
–20
10k
100k
1M
INPUT FREQUENCY (Hz)
T
H
D
(
d
B)
200
100
62
10
TA = 25°C
VDD = 5V
03
15
3
-02
5
Figure 25. THD vs. Analog Input Frequency for Various Source Impedances
Figure 26 shows a graph of THD vs. analog input frequency for
various supply voltages while sampling at 1 MSPS with an SCLK
of 18 MHz. In this case, the source impedance is 10 Ω.
–50
–90
–85
–80
–75
–70
–65
–60
–55
10
100
1000
INPUT FREQUENCY (kHz)
T
H
D
(
d
B)
TA = 25°C
VDD = 2.7V
VDD = 3.6V
VDD = 4.75V
VDD = 5.25V
03
15
3
-02
6
Figure 26. THD vs. Analog Input Frequency for Various Supply Voltages
DIGITAL INPUTS
The digital inputs applied to the AD7441/AD7451 are not limited
by the maximum ratings that limit the analog inputs. Instead,
the digital inputs applied, that is, CS and SCLK, can go to 7 V
and are not restricted by the VDD + 0.3 V limits as on the analog
input. The main advantage of the inputs not being restricted to
the VDD + 0.3 V limit is that power supply sequencing issues are
avoided. If CS or SCLK are applied before VDD, there is no risk
of latch-up as there would be on the analog inputs if a signal
greater than 0.3 V were applied prior to VDD.
REFERENCE
An external source is required to supply the reference to the
AD7441/AD7451. This reference input can range from 100 mV
to VDD. The specified reference is 2.5 V for the power supply
range 2.7 V to 5.25 V. The reference input chosen for an appli-
cation must never be greater than the power supply. Errors in
the reference source result in gain errors in the AD7441/AD7451
transfer function and add to the specified full-scale errors of the
part. A capacitor of at least 0.1 μF must be placed on the VREF
pin. Suitable reference sources for the AD7441/AD7451 include
tion diagram for the VREF pin.
1
AD780
NC
8
2
VIN
NC
7
3
GND
6
4
TEMP
5
OPSEL
TRIM
VOUT
AD7441/
AD7451*
VREF
2.5V
NC
VDD
NC
VDD
NC = NO CONNECT
10nF
0.1F
*ADDITIONAL PINS OMITTED FOR CLARITY.
0
31
53
-0
27
Figure 27. Typical VREF Connection Diagram for VDD = 5 V
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