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參數(shù)資料
| 型號： | AD7476ARTZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 1MSPS LP SOT23-6 |
| 設(shè)計資源： | Output Channel Monitoring Using AD5380 (CN0008) AD5382 Channel Monitor Function (CN0012) AD5381 Channel Monitor Function (CN0013) AD5383 Channel Monitor Function (CN0015) AD5390/91/92 Channel Monitor Function (CN0030) Power off protected data acquisition signal chain using ADG4612 , AD711, and AD7476 (CN0165) |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 17.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-6 |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
| 配用： | EVAL-AD7476ACBZ-ND - BOARD EVALUATION FOR AD7476A |
AD7476/AD7477/AD7478
Rev. F | Page 15 of 24
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SOURCE IMPEDANCE (
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fIN = 200kHz
fIN = 300kHz
fIN = 100kHz
fIN = 10kHz
VDD = 2.7V
fS = 605kSPS
Figure 16. THD vs. Source Impedance for Various Analog Input Frequencies
VDD = 2.35V
VDD = 5.25V
VDD = 2.7V
VDD = 4.75V
VDD = 3.6V
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INPUT FREQUENCY (Hz)
Figure 17. THD vs. Analog Input Frequency, fs = 993 kSPS
VDD = 2.35V
VDD = 3.6V
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INPUT FREQUENCY (Hz)
VDD = 4.75V
VDD = 5.25V
VDD = 2.7V
Figure 18. THD vs. Analog Input Frequency, fs = 605 kSPS
Digital Input
The digital input applied to the AD7476/AD7477/AD7478 is
not limited by the maximum ratings that limit the analog input.
Instead, the digital input applied can go to 7 V and is not
restricted by the VDD + 0.3 V limit as on the analog input. For
example, if the AD7476/AD7477/AD7478 are operated with a
VDD of 3 V, then 5 V logic levels can be used on the digital input.
However, note that the data output on SDATA still has 3 V logic
levels when VDD = 3 V. Another advantage of SCLK and CS not
being restricted by the VDD + 0.3 V limit is that power supply
sequencing issues are avoided. If CS or SCLK is applied before
VDD, there is no risk of latch-up as there is on the analog input
when a signal greater than 0.3 V is applied prior to VDD.
MODES OF OPERATION
Select the mode of operation of the AD7476/AD7477/AD7478
by controlling the (logic) state of the CS signal during a
conversion. The two possible modes of operation are normal
mode and power-down mode. The point at which CS is pulled
high after the conversion has been initiated determines whether
or not the AD7476/AD7477/AD7478 enters power-down mode.
Similarly, if already in power-down, CS can control whether the
device returns to normal operation or remains in power-down.
These modes of operation are designed to provide flexible
power management options. These options can be chosen to
optimize the power dissipation/throughput rate ratio for
different application requirements.
Normal Mode
This mode is intended for fastest throughput rate performance.
Users do not have to worry about power-up times with the
AD7476/AD7477/AD7478 remaining fully powered at all times.
Figure 19 shows the general diagram of the AD7476/AD7477/
AD7478 in normal mode.
The conversion is initiated on the falling edge of CS as de-
scribed in the
section. To ensure the part
remains fully powered up at all times,
CS must remain low until
at least 10 SCLK falling edges have elapsed after the falling edge
of CS. If CS is brought high any time after the tenth SCLK
falling edge, but before the sixteenth SCLK falling edge, the part
remains powered up, but the conversion terminates and SDATA
goes back into three-state. Sixteen serial clock cycles are
required to complete the conversion and access the complete
conversion result. CS may idle high until the next conversion or
may idle low until CS returns high sometime prior to the next
conversion (effectively idling CS low).
Once a data transfer is complete, (SDATA has returned to three-
state), another conversion can be initiated after the quiet time,
tQUIET, has elapsed by again bringing CS low.
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