參數(shù)資料
型號： AD7476AYKSZ-REEL7
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 2.35 V to 5.25 V, 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SC70
中文描述： 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6
封裝： ROHS COMPLIANT, MO-203AB, SC-70, 6 PIN
文件頁數(shù)： 7/24頁
文件大?。?/td> 580K
代理商： AD7476AYKSZ-REEL7
REV. C
AD7476A/AD7477A/AD7478A
–7–
Timing Example 1
Having f
SCLK
= 20 MHz and a throughput of 1 MSPS gives a
cycle time of t
2
+ 12.5 (1/f
SCLK
) + t
ACQ
= 1
μ
s. With t
2
= 10 ns min,
this leaves t
ACQ
to be 365 ns. This 365 ns satisfies the requirement
of 250 ns for t
ACQ
. From Figure 3, t
ACQ
is comprised of 2.5 (1/f
SCLK
)
+ t
8
+ t
QUIET
, where t
8
= 36 ns max. This allows a value of 204 ns
for t
QUIET
,
satisfying the minimum requirement of 50 ns.
CS
SCLK
SDATA
t
2
t
6
t
3
t
4
ZERO
t
7
DB10
t
5
t
8
t
CONVERT
t
QUIET
ZERO
ZERO
DB11
DB2
DB1
DB0
B
THREE-STATE
THREE-
STATE
Z
4 LEADING ZEROS
1
2
3
4
5
13
14
15
16
t
1
Figure 2. AD7476A Serial Interface Timing Diagram
CS
SCLK
t
2
t
CONVERT
B
1
2
3
4
5
13
14
15
16
C
t
8
t
QUIET
t
ACQ
12.5(1/fSCLK)
1/THROUGHPUT
Figure 3. Serial Interface Timing Example
Timing Example 2
Having f
SCLK
= 5 MHz and a throughput of 315 kSPS gives a
cycle time of t
2
+ 12.5 (1/f
SCLK
) + t
ACQ
= 3.174
μ
s. With t
2
=
10 ns min, this leaves t
ACQ
to be 664 ns. This 664 ns satisfies
the requirement of 250 ns for t
ACQ
. From Figure 3, t
ACQ
is
comprised of 2.5 (1/f
SCLK
) + t
8
+ t
QUIET
, t
8
= 36 ns max. This
allows a value of 128 ns for t
QUIET
,
satisfying the minimum
requirement of 50 ns. As in this example and with other slower
clock values, the signal may already be acquired before the
conversion is complete, but it is still necessary to leave 50 ns
minimum t
QUIET
between conversions. In Example 2, the
signal should be fully acquired at approximately Point C in
Figure 3.
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