參數(shù)資料
型號(hào)： AD7477AAKSZ-REEL7
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： GT 12C 6#12 6#16 PIN RECP WALL
中文描述： 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6
封裝： ROHS COMPLIANT, MO-203AB, SC-70, 6 PIN
文件頁(yè)數(shù)： 14/24頁(yè)
文件大?。?/td> 580K
代理商： AD7477AAKSZ-REEL7
REV. C
–14–
AD7476A/AD7477A/AD7478A
CIRCUIT INFORMATION
The AD7476A/AD7477A/AD7478A are fast, micropower,
12-/10-/8-bit, single-supply A/D converters, respectively. The
parts can be operated from a 2.35 V to 5.25 V supply. When
operated from either a 5 V supply or a 3 V supply, the AD7476A/
AD7477A/AD7478A are capable of throughput rates of 1 MSPS
when provided with a 20 MHz clock.
The AD7476A/AD7477A/AD7478A provide the user with an
on-chip, track-and-hold A/D converter and a serial interface
housed in a tiny 6-lead SC70 or 8-lead MSOP package, which
offer the user considerable space-saving advantages over alterna-
tive solutions. The serial clock input accesses data from the part
but also provides the clock source for the successive-approximation
A/D converter. The analog input range is 0 V to V
DD
. The ADC
does not require an external reference or an on-chip reference.
The reference for the AD7476A/AD7477A/AD7478A is derived
from the power supply and thus gives the widest dynamic input
range.
The AD7476A/AD7477A/AD7478A also feature a power-down
option to allow power saving between conversions. The power-
down feature is implemented across the standard serial interface,
as described in the Modes of Operation section.
CONVERTER OPERATION
The AD7476A/AD7477A/AD7478A is a successive-approximation,
analog-to-digital converter based around a charge redistribution
DAC. Figures 4 and 5 show simplified schematics of the ADC.
Figure 4 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in Position A, the comparator is held in a
balanced condition, and the sampling capacitor acquires the
signal on V
IN
.
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
COMPARATOR
SW2
SAMPLING
CAPACITOR
ACQUISITION
PHASE
SW1
A
B
AGND
V
DD
/2
V
IN
Figure 4. ADC Acquisition Phase
When the ADC starts a conversion, see Figure 5, SW2 will open and
SW1 will move to Position B, causing the comparator to become
unbalanced. The control logic and the charge redistribution
DAC are used to add and subtract fixed amounts of charge from
the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code. Figure 6 shows the ADC transfer function.
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
COMPARATOR
SW2
SAMPLING
CAPACITOR
CONVERSION
PHASE
SW1
A
B
AGND
V
DD
/2
V
IN
Figure 5. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7476A/AD7477A/AD7478A is
straight binary.
The designed code transitions occur at the successive integer
LSB values, i.e., 1 LSB, 2 LSB, and so on. The LSB size is
V
DD
/4096 for the AD7476A, V
DD
/1024 for the AD7477A, and
V
DD
/256 for the AD7478A. The ideal transfer characteristic for
the AD7476A/AD7477A/AD7478A is shown in Figure 6.
000...000
0V
A
ANALOG INPUT
111...111
111...110
000...001
000...010
111...000
011...111
1LSB = V
DD
/256 (AD7478A)
1LSB
+V
DD
– 1LSB
1LSB = V
DD
/1024 (AD7477A)
1LSB = V
DD
/4096 (AD7476A)
Figure 6. AD7476A/AD7477A/AD7478A
Transfer Characteristic
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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AD7477AARMZ 功能描述:IC ADC 10BIT 1MSPS 8-MSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6
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