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參數(shù)資料
| 型號： | AD7490 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | 16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP |
| 中文描述： | 16路，1 MSPS的12位序列ADC的28引腳TSSOP |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 2255K |
| 代理商： | AD7490 |
AD7490
–17–
REV. A
CS
SCLK
DOUT
DIN
1
2
3
4
5
6
13
14
t
5
15
16
WRITE
SEQ
ADD3
ADD2
ADD1
ADD0
DONTC
DONTC
DONTC
ADD3
ADD2
ADD1
ADD0
DB11
t
10
DB10
DB2
DB1
DB0
t
8
t
CONVERT
t
2
t
3
t
9
t
4
t
7
t
11
B
FOUR IDENTIFICATION BITS
THREE-
STATE
THREE-
STATE
t
QUIET
t
6
t
3
b
Figure 17. Serial Interface Timing Diagram
CS
SCLK
DOUT
DIN
1
2
3
4
5
6
13
14
t
5
15
16
ADD3
ADD2
ADD1
ADD0
DB11
DB10
DB2
DB1
DB0
t
8
t
CONVERT
t
3
t
9
t
10
t
4
t
7
t
11
FOUR IDENTIFICATION BITS
THREE-
STATE
THREE-
STATE
C
V
IN
0
V
IN
1
V
IN
2
V
IN
3
V
IN
4
V
IN
5
V
IN
13
V
IN
14
V
IN
15
t
6
t
2
Figure 18. Writing to Shadow Register Timing Diagram
supplies are applied, the Control Register will contain the correct
information and valid data will result from the next conversion.
Therefore, to ensure the part is placed into the correct operating
mode when supplies are first applied to the AD7490, the user must
first issue two serial write operations with the DIN line tied
high. On the third conversion cycle, the user can then write to the
Control Register to place the part into any of the operating modes.
The user should not write to the Shadow Register until the fourth
conversion cycle after the supplies are applied to the ADC in
order to guarantee the Control Register contains the correct data.
If the user wishes to place the part into either Normal Mode or
Full Shutdown Mode, the second dummy cycle with DIN tied
high can be omitted from the three dummy conversion operation
outlined in Figure 16.
SERIAL INTERFACE
Figure 17 shows the detailed timing diagram for serial interfacing
to the AD7490. The serial clock provides the conversion clock
and also controls the transfer of information to and from the
AD7490 during each conversion.
The
CS
signal initiates the data transfer and conversion process.
The falling edge of
CS
puts the track and hold into hold mode,
takes the bus out of three-state, and the analog input is sampled
at this point. The conversion is also initiated at this point and
will require 16 SCLK cycles to complete. The track and hold
will go back into track on the 14th SCLK falling edge as shown in
Figure 17 at point B, except when the write is to the Shadow
Register, in which case the track and hold will not return to
track until the rising edge of
CS
, i.e., point C in Figure 18. On
the 16th SCLK falling edge, the DOUT line will go back into
three-state (assuming the WEAK/
TRI
Bit is set to 0). Sixteen
serial clock cycles are required to perform the conversion process
and to access data from the AD7490. The 12 bits of data are
preceded by the four channel address bits ADD3 to ADD0,
identifying which channel the conversion result corresponds to.
CS
going low provides address bit ADD3 to be read in by the
microprocessor or DSP. The remaining address bits and data bits
are then clocked out by subsequent SCLK falling edges beginning
with the second address bit ADD2; thus the first SCLK falling
edge on the serial clock has address bit ADD3 provided and also
clocks out address bit ADD2. The final bit in the data transfer is
valid on the 16th falling edge, having being clocked out on the
previous (15th) falling edge.
Writing of information to the Control Register takes place on
the first 12 falling edges of SCLK in a data transfer, assuming the
MSB, i.e., the WRITE Bit, has been set to 1. If the Control Register
is programmed to use the Shadow Register, writing of information
to the Shadow Register will take place on all 16 SCLK falling
edges in the next serial transfer (see Figure 18). The Shadow Reg-
ister will be updated upon the rising edge of
CS
and the track and
hold will begin to track the first channel selected in the sequence.
If the WEAK/
TRI
Bit in the Control Register is set to 1, rather than
returning to true three-state upon the 16th SCLK falling edge,
the DOUT line will instead be pulled weakly to the logic level
corresponding to ADD3 of the next serial transfer. This is done
to ensure that the MSB of the next serial transfer is set up in time
for the first SCLK falling edge after the
CS
falling edge. If the
WEAK/
TRI
Bit is set to 0 and the DOUT line has been in true
three-state between conversions, then depending on the particular
DSP or microcontroller interfacing to the AD7490, address bit
ADD3 may not be set up in time for the DSP/micro to clock it in
successfully. In this case, ADD3 would only be driven from the
falling edge of
CS
and must then be clocked in by the DSP on the
following falling edge of SCLK. However, if the WEAK/
TRI
Bit
had been set to 1, then although DOUT is driven with address bit
ADD3 since the last conversion, it is nevertheless so weakly driven
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