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參數(shù)資料
| 型號： | AD7524JP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | CMOS 8-Bit Buffered Multiplying DAC |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.5 us SETTLING TIME, 8-BIT DAC, PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 162K |
| 代理商： | AD7524JP |
AD7524
REV. B
–4–
WRIT E MODE
When
CS
and
WR
are both LOW, the AD7524 is in the
WRIT E mode, and the AD7524 analog output responds to data
activity at the DB0–DB7 data bus inputs. In this mode, the
AD7524 acts like a nonlatched input D/A converter.
HOLD MODE
When either
CS
or
WR
is HIGH, the AD7524 is in the HOLD
mode. T he AD7524 analog output holds the value correspond-
ing to the last digital input present at DB0–DB7 prior to
WR
or
CS
assuming the HIGH state.
MODE SE LE CT ION T ABLE
CS
WR
Mode
DAC Response
L
L
Write
DAC responds to data bus
(DB0–DB7) inputs.
H
X
Hold
Data bus (DB0–DB7) is
Locked Out:
X
H
Hold
DAC holds last data present
when
WR
or
CS
assumed
HIGH state.
L = Low State, H = High State, X = Don't Care.
WRIT E CY CLE T IMING DIAGRAM
Figure 3. Supply Current vs. Logic Level
T ypical plots of supply current, I
DD
, versus logic input voltage,
V
IN
, for V
DD
= +5 V and V
DD
= +15 V are shown above.
CIRCUIT DE SCRIPT ION
CIRCUIT INFORMAT ION
T he AD7524, an 8-bit multiplying D/A converter, consists of a
highly stable thin film R-2R ladder and eight N-channel current
switches on a monolithic chip. Most applications require the
addition of only an output operational amplifier and a voltage
or current reference.
T he simplified D/A circuit is shown in Figure 1. An inverted
R-2R ladder structure is used—that is, the binarily weighted
currents are switched between the OUT 1 and OUT 2 bus lines,
thus maintaining a constant current in each ladder leg indepen-
dent of the switch state.
Figure 1. Functional Diagram
E QUIVALE NT CIRCUIT ANALY SIS
T he equivalent circuit for all digital inputs LOW is shown in
Figures 2. In Figure 2 with all digital inputs LOW, the refer-
ence current is switched to OUT 2. T he current source I
LEAK AGE
is composed of surface and junction leakages to the substrate
1
256
current source represents a constant 1-bit cur-
rent drain through the termination resistor on the R-2R ladder.
T he “ON” capacitance of the output N-channel switches is
120 pF, as shown on the OUT 2 terminal. T he “OFF” switch
capacitance is 30 pF, as shown on the OUT 1 terminal. Analysis
of the circuit for all digital inputs high is similar to Figure 2
however, the “ON” switches are now on terminal OUT 1, hence
the 120 pF appears at that terminal.
while the
Figure 2. AD7524 DAC Equivalent Circuit—All Digital
Inputs Low
INT E RFACE LOGIC INFORMAT ION
MODE SE LE CT ION
AD7524 mode selection is controlled by the
CS
and
WR
inputs.
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| AD7524JR | 功能描述:IC DAC 8BIT MULTIPLYING 16-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD7524JR-REEL | 功能描述:IC DAC 8BIT MULTIPLYING 16-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,400 系列:- 設(shè)置時間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應(yīng)商設(shè)備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率（每秒）:* |
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